ECE 154: Intro. to Computer Architecture


Behrooz Parhami: 2007/06/19  ||  E-mail:  ||  Problems:

Other contact info at: Bottom of this page  ||  Go up to: B. Parhami's course syllabi or his home page


On June 19, 2007, Professor Parhami's UCSB ECE website moved to a new location. For an up-to-date version of this page, visit it at the new address:

Link to  previous offerings of ECE 154
Winter quarter 2007 offering of ECE 154

This area is reserved for important course announcements:  2007/03/26: Course grades have been submitted to the Registrar. Final exam grades: Range [34, 84], Mean 60, Median 59, SD 11. Have a great spring break!

2007/03/07: A sample final exam and suggested problems from Chapter 21-24 have been added to this page. The instructor and TAs will maintain their normal office hours during the finals week (3/19-23). In addition, the following office hours have been added for Friday, 3/23 -- 11:00-12:00 (JK, ECI Lab), 2:00-3:00 (SC, ECI Lab), 5:00-6:00 (BP, 5155 HFH).

2007/03/03: Exam grades: [Min, Max], Mean, Median, SD -- MT1: [49, 89], 68, 68, 10 --  MT2: [61, 99], 85, 87, 10. The seventh homework assignment has been posted below a few days ahead of schedule to give you more time for working on it, given the rush of end-of-quarter assignments, projects, and exams.


ECE 154 – Introduction to Computer Architecture, University of California, Santa Barbara, Winter Quarter 2007, Enrollment Code  11486 (for codes pertaining to discussion sessions, see "Meetings" below)

Catalog entry:   

154. Introduction to Computer Architecture. (4) PARHAMI. Prerequisite: ECE 152A with a minimum grade of C-; open to EE, computer engineering, and computer science majors only. Not open for credit to students who have completed Computer Science 154. Lecture, 3 hours; discussion, 1 hour.  The computer design space. Methods of performance evaluation. Machine instructions and assembly language. Variations in instruction set architecture. Design of arithmetic/logic units. Data path and control unit synthesis. Pipelining and multiple instruction issue. Hierarchical memory systems. Input/output and interfacing. High-performance systems, including multiprocessors and multicomputers.


Behrooz Parhami, Room 5155 Harold Frank Hall (Engineering I), Phone 805-893-3211, E-mail


Justin Kane, ; H.-M. Sherman Chang,


Lectures  MW 3:30-4:45, North Hall 1006

Discussion, option 1 – F 1:00-1:50, Phelps 1508 (Chang, enrollment code 11494)

Discussion, option 2 – F 11:00-11:50, Girvetz 1112 (Kane, enrollment code 11502)

Discussion, option 3 – F 12:00-12:50, Phelps 3519 (Kane, enrollment code 11510)

Discussion, option 4 – F 2:00-2:50, Bldg 387 Room 103 (Chang, enrollment code 11528)


Instructor’s office hours, held in Room 5155 HFH – M 11:30-1:00, W 12:30-2:00

TA office hours, held in the ECI Lab, Room 1140 HFH – T 5-6 PM (Chang); R 12-2 PM (Kane) and 5-6 PM (Chang)


Computer architecture is the study/specification of (digital) computer systems at the interface of hardware and software. Computer architecture is driven from the software side by user needs in terms of functions and speed and from the hardware side by technological innovations and constraints. ECE 154 introduces you to this exciting field and makes you an informed computer user who understands basic architectural features as well as their cost/performance implications. The programmer's view of the instruction set and user interface are considered along with memory organization, addressing methods, input/output, implementation of control, and a multitude of performance issues and computation speedup methods. ECE 154 also prepares you for participation in computer design efforts and for learning the advanced implementation methods and technologies used in vector supercomputers (ECE 254A), parallel processors (ECE 254B), and distributed systems (ECE 254C).


Familiarity with logic design and digital circuits (ECE 152A or equivalent). Fundamentals of digital logic circuits will be reviewed in 1-2 refresher-type lecture(s).


Required textbook – B. Parhami, Computer Architecture: From Microprocessors to Supercomputers, Oxford University Press, 2005. Click on the link above to see the textbook's Web page which has downloadable PowerPoint presentations, a list of errors, and other material. Publisher's list price $82, UCSB Bookstore price $82.

Useful book – D.A. Patterson & J.L. Hennessy, Computer Organization & Design: The Hardware/Software Interface, Morgan Kaufmann, 3rd ed., 2005.

Electronic Resources at UCSB (electronic journals, collections, etc.) (research guide in ECE)


Students will be evaluated based on these 3 components with the given weights:


20% -- Seven homework assignments posted on the course website by specified dates and due in a homework box in about one week. Homework descriptions appear below, after the course calendar.


40% -- Two closed-book midterm exams (see the course calendar for date, time, and coverage).


40% -- Closed-book final exam (see the course calendar for place, date, time, and coverage).


Course lectures, homework assignments, and exams have been scheduled as follows. This schedule will be strictly observed. About half of the lectures have been marked as important or very important. These lectures cover key concepts that constitute the core of ECE 154.



Subject of Lecture or Discussion

HW (chap's)

Special Notes

M 1/8   


Course intro, review of logic circuits  



W  1/10   


Computer performance

HW1 (1-3)

Very important lecture

F 1/12  


(Discussion: Logic circuits + technology)



M 1/15   


No lecture: Martin Luther King, Jr., Holiday



W 1/17   


MiniMIPS instructions and addressing

HW2 (4)


F 1/19   


(Discussion: Computer performance + HW1)

HW1 due


M 1/22 


MiniMIPS (cont.), assembly programs


W 1/24  

8 ISA variations, CISC, RISC, URISC

HW3 (5-7)


F 1/26 5-8  (Discussion: Instruction sets + HW2) HW2 due  

M 1/29 


Number representation and basic adders


W 1/31   


Fast addition and multifunction ALUs

HW4 (8-10)

Important lecture

F 2/2 9-10 (Discussion: Number rep + addition + HW3) HW3 due  

M 2/5  


1st midterm exam, in our regular classroom



W 2/7   


Stages of instruction execution


Important lecture

F 2/9 4-10 (Discussion: 1st midterm exam + HW4) HW4 due  
M 2/12 14 Control unit synthesis   Important lecture
W 2/14 15 Pipelined data paths

HW5 (13-14)

Important lecture
F 2/16 13-14 (Discussion: Data path and control)     

M 2/19  


No Lecture: President's Day Holiday

W 2/21


Pipeline performance limits

HW6 (15-16)

Important lecture

F 2/23   


(Discussion: Pipelining + HW5)

HW5 due


M 2/26   


2nd midterm exam, in our regular classroom



W 2/28   

17, 19  

Main and mass  memory concepts



F 3/2

17, 19 

(Discussion: Memory system + HW6)

HW6 due  

M 3/5


Cache memory

Very important lecture

W 3/7


Virtual memory and paging

HW7 (17-20)


F 3/9

18, 20 

(Cache and virtual memory)



M 3/12 


Input/output devices and programming



W 3/14 


Buses, interfacing, and interrupts


Sample final handed out

F 3/16 21-24 (Discussion: I/O, buses, interrupts + HW7) HW7 due  
Sat 3/24


Final exam, 12:00-3:00 PM, NH 1006



Homework: General Requirements

Deposit solutions in ECE 154 homework box (Room 3120 HFH) before 10 AM on due date.

Late homework will not be accepted, so plan to start work on your assignments early.

Use a cover page that includes your name, course and assignment number for your solutions.

Staple the sheets and write your name on top of every sheet in case sheets are separated.

Although some cooperation is permitted, direct copying will have severe consequences.  

Homework 1: Logic design and computer technology (ch. 1-3, due F 1/19/2007, 10:00 AM)

Do the following problems from the textbook (20 points each): 1.7, 1.9d, 2.4a, 2.8a, 3.16

Grades: Range = [65, 100], Mean = 81, Median = 85, SD = 12

Homework 2: Computer performance (ch. 4, due F 1/26/2007, 10:00 AM)

Do the following problems from the textbook: 4.6 (20 pts.), 4.7 (20 pts.), 4.9 (25 pts.), 4.17 (10 pts.), 4.20 (25 pts.)

Grades: Range = [40, 100], Mean = 78, Median = 83, SD = 16

Homework 3: Instructions and assembly language (ch. 5-7, due F 2/2/2007, 10:00 AM)

Do the following problems from the textbook: 5.7 (10 pts.), 5.8 (10 pts.), 5.17 (25 pts.), 6.12 (20 pts.), 6.13 (25 pts.), 7.4c (10 pts.)

Grades: Range = [70, 100], Mean = 92, Median = 95, SD = 9

Homework 4: ISA variations and computer arithmetic (ch. 8-10, due F 2/9/2007, 10:00 AM)

Do the following problems from the textbook, plus problem 10.A (15 pts.), defined below: 8.9 (20 pts.), 8.10 (20 pts.), 9.9c (10 pts.), 9.16abc (15 pts.), 10.21 (20 pts.)

Grades: Range = [70, 100], Mean = 92, Median = 95, SD = 9

Problem 10.A -- Alternative carry networks: Consider the following Kogge-Stone carry network for an 8-bit adder. By labeling its lines in a manner similar to Fig. 10.11, verify that the network does indeed produce the required carries. Then, compare the new network with the Brent-Kung network of Fig. 10.11 with respect to cost/complexity (carry-operator count) and latency (carry-operator levels). Challenge question (optional): Can you write general formulas for the complexity and latency of the new network with k inputs, assuming that k is a power of 2?

Homework 5: Data path design and control unit (ch. 13-14, due F 2/23/2007, 10:00 AM)

Do the following problems from the textbook: 13.3 (25 pts.), 13.7 (25 pts.), 13.12 (20 pts.), 14.5 (10 pts.), 14.7 (20 pts.)

Grades: Range = [55, 100], Mean = 96, Median = 99, SD = 9

Homework 6: Pipelining and its limits (ch. 15-16, due F 3/2/2007, 10:00 AM)

Do the following problems from the textbook: 15.6e (20 pts.), 15.14b (10 pts.), 15.16 (15 pts.), 16.1 (15 pts.), 16.4 (20 pts.), 16.10ab (20 pts.)

Grades: Range = [60, 100], Mean = 94, Median = 97, SD = 8

Homework 7: Memory system design (ch. 17-20, due F 3/16/2007, 10:00 AM)

Do the following problems from the textbook: 17.3 (20 pts.), 18.4 (15 pts.), 18.5ac (20 pts.), 19.7d (15 pts.), 20.1a (10 pts), 20.4 (20 pts)

Grades: Range = [70, 100], Mean = 88, Median = 90, SD = 7

Suggested problems (ch. 21-24, for practice only, not to be turned in)

Do the following problems from the textbook: 21.8, 21.9 [Correction: Example 21.2 is intended], 22.1, 22.5, 22.9, 23.4, 24.2, 24.11

Sample Midterm Exam

The following is meant to indicate the types and levels of problems in the midterm, rather than the coverage (which is outlined in the lecture schedule and below). This particular exam covered up to the end of Chapter 12 of the textbook and was 105 minutes long (our two midterms will be 85 minutes each). Table 6.2 of the text was appended to the end of the exam for reference in solving Problem 3.

Problem 1 [15 points]. Defining concepts and terms -- Define each of the following concepts/terms precisely and concisely within the space provided (about 1.5 inch per term) [3 points each]: Decoder; PC-relative addressing; Pseudoinstruction; Assembler directive; Directed rounding.

Problem 2 [25 points]. Amdahl's law -- Problem 4.16 in the text [part a, 15 points; part b, 10 points]

Problem 3 [20 points] Machine instructions -- Problem 7.3 in the text, parts d and g [10 points each]

Problem 4 [20 points] Multifunction ALU -- Consider the following multifunction ALU studied in class. Specify the control signal values that are needed for executing the following two instructions. [10 points each]  [Fig. 10.19 of the text goes here] (a) sll. (b) slt.

Problem 5 [20 points] Shift-add binary hardware multiplier -- In the following diagram of a radix-2 hardware multiplier, explain: [Fig. 11.4 of the text goes here] (a) [6 points] Why the register holding the multiplier y can be merged with the one holding the doublewidth partial product z(j). (b) [6 points] The role of the multiplexer. (c) [8 points] How separate cycles or phases for loading the doublewidth partial product register and shifting it to the right can be avoided.

Sample Final Exam

The following is meant to indicate the types and levels of problems in the final, rather than the coverage (which is outlined in the lecture schedule and below). This particular exam covered up to the end of Chapter 24 of the textbook and was 150 minutes long. The single midterm had included up to the end of Chapter 12 in the textbook.

Problem 1 [16 points]. Defining concepts and terms -- Define each of the following concepts/terms precisely and concisely within the space provided (about 1 inch per term) [2 points each]: Bus arbitration; Conflict miss; Delayed branch; Interrupt handler; Pseudoinstruction; Set-associative cache; TLB.

Problem 2 [15 points] Computer arithmetic -- Problem 11.10a in the text.

Problem 3 [12 points] Processor data path -- Problem 13.2b in the text.

Problem 4 [16 points] Control unit design -- The following diagram shows a microprogrammed implementation of control unit functions [Fig. 14.7 of the text goes here]. (a) Does this diagram represent a single-cycle or multicycle implementation? Why? (b) What are the roles of the dispatch ROMs? (c) How are the values of the "Sequence control" signals, that control the 4-input mux, decided? (d) Name and describe two of the control signals that go from the microinstruction register to the data path section (choose any two and describe their functions briefly).

Problem 5 [15 points] Pipelining -- In the following diagram, a pipelined data path for MicroMIPS and some of its controls are shown [Fig. 15.10 of the text goes here]. Explain the roles of: (a) The control signals that are stored in the bottom part of the pipeline registers. (b) The multiplexer that appears below the SE circle, next to the register file. (c) The multiplexer located above the program counter.

Problem 6 [16 points] Memory hierarchy -- Example 20.3 in the text.

Problem 7 [10 points] Input/Output -- Example 22.5 in the text.

Midterm and Final Exam Preparation

The following includes topics that will be emphasized, as well as list of exclusions from the midterm exams (Chapters 4-10 for midterm 1, Chapters 13-16 for midterm 2) and final exam (Chapters 4-24). All sections not specifically excluded are required, even if they are not covered in class.

Chapters 1-3 -- No direct problem or question, but you need to know (and be able to define) concepts such as tristate buffers, multiplexers, register files, and so on, used to explain the topics that follow.

Chapter 4 -- Computer performance: problem likely on CPI calculation, performance enhancement (Amdahl's law), instruction mix, and/or benchmarks.

Chapters 5-8 -- Instruction-set architecture: You do not need to memorize instruction codes or formats. Any problem in this area will be accompanied by a reference table providing a list of codes and formats if required. Ignore Sections 7.5, 7.6, and 8.4.

Chapters 9-10 -- Computer arithmetic: problem likely on 2's-complement numbers, number radix conversion, floating-point number formats, shift/logical operations (including distinction between arithmetic and logical shifts), adders and ALUs.

Chapters 13-14 -- Data path and control: problem very likely on control unit structure, control signal generation, multicycle instruction execution, and control state machine. Section 14.5 is excluded.

Chapter 15-16 -- Pipelining: problem very likely on pipeline bubbles (how to insert or avoid them), pipeline control, data hazards, data forwarding, control hazards, delayed branch, and/or branch prediction.

The following apply to the final exam, which will include material from the preceding chapters as well, but to a lesser degree.

Chapters 17-20 -- Memory hierarchy: problem very likely on the need for memory hierarchy, cache memory concepts (levels 1 and 2), miss/hit rate, average memory access time, compulsory/capacity/conflict misses, mapping schemes, virtual memory, page table, and/or TLB. Sections 17.5, 19.5, and 19.6 are excluded.

Chapters 21-24 -- Input/output and interfacing: problem possible on memory-mapped, polled, or interrupt-driven I/O, buses, and interrupts. Sections 21.5, 21.6, 22.6, 23.5, 23.6, 24.5, and 24.6 are excluded.

Chapters 25-28 -- Advanced architectures: no problem or question.  

Return to: Top of this page  ||  Go up to: B. Parhami's course syllabi or his home page


Dr. Behrooz Parhami, Professor

                     Office phone: +1 805 893 3211
E-mail:                 Messages: +1 805 893 3716
Dept. Electrical & Computer Eng.                  Dept. fax: +1 805 893 3262
Univ. of California, Santa Barbara                Office: Room 5155 Eng. I
Santa Barbara, CA 93106-9560 USA                      Deliveries: Room 4155 Eng. I