This package implements a DMA controller using Bluespec
SystemVerilog.  The first model shows a simple 1 channel, 1 port
model.  There are four refinements of this model.

V1 - Rule based DMA controller allowing pipelined requests
V2 - 2 memory port, allowing pipelined and concurrent read and write
requests
V3 - Modified version of V2 showing Bluespec's elaboration features
V4 - 2 channels, 2 ports, concurrent and pipelined transactions

Each example is in its own directory.  Each directory contains the
following files:
DMA.bsv - the DMA model
Testbench.bsv - the testbench
sysTestBench.out.expected -  expected simulation results
Socket_IFC.bsv - defines a simple socket protocol, interfaces,
structures and utility functions
EdgeFIFOs.bsv - some specialized FIFOs used throughout the design
Targets.bsv - a simple target module used for testing
Makefile - usual
DMA.bspec - project file for use with the development workstation