ADVANCED COMPUTER ARCHITECTURE

ECE 154B, Winter 2023

A. Class Information

Instructor: Dmitri Strukov

Lectures: 9:30 am to 10:45 am on Tuesday and Thursday, Girvetz Hall 2119

Email: strukov at ece dot ucsb dot edu

Office Hours: by appointment via zoom or in person

Teaching Assistant: Ethan Sifferman

Email: ethanjsifferman at ece dot ucsb dot edu

Office Hours: TBA

Recommended Textbook (but not necessary)

H&H - Digital Design and Computer Architecture, RISC-V Edition: RISC-V Edition 1st Edition, David Harris and Sarah Harris, Elsevier, 2021, ISBN-10: 0128200642

H&P - Computer Architecture: A Quantitative Approach, John L. Hennessy and David A. Patterson, Sixth Edition, Morgan Kaufmann, 2019, ISBN: 978-0-12-811905-1

S&L - Modern Processor Design: Fundamentals of Superscalar Processors, John Paul Shen and Mikko H. Lipasti, Waveland Press, 2013, ISBN: 1478607831

Office Hours Zoom: https://ucsb.zoom.us/j/99516654272

Grading: The grade is based on successful completion of projects. No midterms / finals.

Piazza: piazza.com/ucsb/winter2023/advancecomputerarchitecture

The access code was sent to registered students via email. If you are a new student, send request to the instructor to get access code.

B. Class Topics and Tentative Schedule

· RISC-V (rationale, basic ISA, advanced ISA topics) - ~1.5 weeks

· Memory hierarchy (virtual memory, advanced techniques) - ~ 2.5 weeks

· Instruction level parallelism (dynamic scheduling, speculation, superscalar, out of order execution, branch prediction) - ~ 2.5 weeks

· Data level parallelism (vector processors and SIMD) - ~0.5 weeks

· Thread level parallelism (shared-memory architectures, synchronization, cache coherence) - ~1 week

· Graphics processing units - ~1 week, time permitted

· Historical trends, computer economics, and fundamental challenges - ~1 week, time permitted

C. Project Assignments

The course work involves 6 projects related to the RTL design and simulation of RISC-V processor components using SystemVerilog language. An open source CVA6 core is used as a basis for the labs. Project description and the due dates will be announced on Piazza.

D. Class Materials and Reading

Slides are password protected. Access credentials were announced on Piazza.

Week #1:

- Reading:

o Chapter 6 from H&H

o RISC-V unprivileged ISA specification document - Volume 1 pdf at https://riscv.org/technical/specifications/

§ Focus on Chapters 1, 2, 4, 16, 28 for now

- RISC-V greensheet: version 1, version 2 (from H&H)

- Slides: Logistics [updated 01/16], RISC-V basics

Week #2:

- Optional Reading: Chapter 9 from S&L

- Slides: Branch Predictors [updated 01/23]

Week #3:

- Optional Reading: Appendix B from H&P

- Slides: Memory Hierarchy part 1 [updated 01/31]

Week #4:

- Optional Reading: Chapter 2 from H&P

- Slides: Memory Hierarchy part 2 [updated 01/31]

Week #5:

- Optional Reading: Chapter 2 from H&P

- Slides: Memory Hierarchy part 3 [updated 02/14]

Week #6:

- Optional Reading: Appendix C and Chapter 3 from H&P

- Slides: ILP part 1 [updated 02/21]

Week #7:

- Optional Reading: Chapter 3 from H&P

- Slides: ILP part 2 [updated 02/28]

Week #8:

- Optional Reading: Chapter 4 from H&P

- Slides: DLP [updated 03/09]

Week #9:

- Optional Reading: Chapter 5 from H&P

- Slides: Multithreading and multiprocessing part 1, part 2 [updated 03/14], part 3

Week #10:

- Slides: Memory consistency, Historical trends and outlook

Last updated: 03/20/23