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| − | ==Process Issues and Defects== | + | ==Process Recipes and Equipment== |
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| | {| border="3" | | {| border="3" |
| − | |+ '''Hybrid Silicon Process'''
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| | |- style="background:red; color:white" | | |- style="background:red; color:white" |
| − | ! Process Step!! Issue or Defect !! Link | + | ! Equipment!! Recipes!! |
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| − | | [[Initial wafer check]] || || || | + | | [[ICP 1]] || |
| − | |-
| + | |
| − | | [[Dice and cleave]] || || ||
| + | |
| − | |-
| + | |
| − | | [[SOI waveguide]] || || ||
| + | |
| − | |-
| + | |
| − | | [[SOI grating]] || || ||
| + | |
| − | |-
| + | |
| − | | [[SOI actives]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Vertical channel]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Protection layer]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Quantum well intermixing]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Wafer bonding]] || Bubbles,Poor Bond, Edge Issues || ||
| + | |
| − | |-
| + | |
| − | | [[Gap fill]] || || ||
| + | |
| − | |-
| + | |
| − | | [[P-mesa]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Lower SCH]] || || ||
| + | |
| − | |-
| + | |
| − | | [[N-InP]] || || ||
| + | |
| − | |-
| + | |
| − | | [[N-metal]] || || ||
| + | |
| − | |-
| + | |
| − | | [[P-metal]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Ion implantation]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Via]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Probe metal]] || || ||
| + | |
| − | |-
| + | |
| − | | [[Remove III/V in gap]] || || ||
| + | |
| | |- | | |- |
| − | | [[Dice and polish]] || || || | + | | [[ICP 2]] || |
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