Difference between revisions of "CaseList"

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(Process Recipes and Equipment)
 
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==Process Issues and Defects==
 
  
{| border="3"
 
|+ '''Hybrid Silicon Process Modules'''
 
|- style="background:red; color:white"
 
! Process Step!! Issue or Defect !!  Link                 
 
|-
 
| [[Initial wafer check]] ||   ||   ||  
 
|-
 
| [[Dice and cleave]] ||   ||   ||  
 
|-
 
| [[SOI waveguide]] ||   ||   ||  
 
|-
 
| [[SOI grating]] ||   ||   ||  
 
|-
 
| [[SOI actives]] ||   ||   ||  
 
|-
 
| [[Vertical channel]] ||  ||   ||  
 
|-
 
| [[Protection layer]] ||   ||   ||  
 
|-
 
| [[Quantum well intermixing]] ||   ||   ||  
 
|-
 
| [[Wafer bonding]] ||   ||   ||  
 
|-
 
| [[Gap fill]] ||   ||   ||  
 
|-
 
| [[P-mesa]] ||   ||   ||  
 
|-
 
| [[Lower SCH]] ||  ||   ||  
 
|-
 
| [[N-InP]] ||   ||   ||  
 
|-
 
| [[N-metal]] ||   ||   ||  
 
|-
 
| [[P-metal]] ||   ||   ||  
 
|-
 
| [[Ion implantation]] ||   ||   ||  
 
|-
 
| [[Via]] ||   ||   ||  
 
|-
 
| [[Probe metal]] ||   ||   ||  
 
|-
 
| [[Remove III/V in gap]] ||  ||   ||  
 
|-
 
| [[Dice and polish]] ||   ||   ||  
 
|-
 
| [[Initial standard wafer testing]] ||   ||   ||  
 
|-
 

Latest revision as of 12:40, 26 November 2012