Difference between revisions of "Wafer Table (old)"

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|+ '''SOI wafer table'''
 
|+ '''SOI wafer table'''
 
|- style="background:red; color:white"
 
|- style="background:red; color:white"
−
! Wafer ID !! Layerstack !! Data and spec-sheet !! Number bought !! Number remaining !! Supplier !! Design/simulation results
+
! Wafer ID !! Substrate(um) !! BOX(um) !! Device layer (um) !! Details of device layer !! # bought !! # remaining !! Supplier !! Note
 
|-  
 
|-  
−
| 1I29437.1 || 675um Si, 1um SiO2, 0.2um Si 1E14 B, 0.5um Si 1E10||   || 21 || 18 || SOITEC+LSRL ||  
+
| 1I29437.1 || 675 || 1 || 0.7 || 0.2um 1E14 B, 0.5um 1E10|| 21 || 18 || SOITEC+LSRL ||  
 
|-
 
|-
−
| 1I29437.1 || 675um Si, 1um SiO2, 0.2um Si 1E14 B, 0.2um Si 1E10 ||   || 4 || 0 || SOITEC+LSRL ||  
+
| 1I29437.1 || 675 || 1 || 0.4 || 0.2um 1E14 B, 0.2um 1E10|| 4 || 0 || SOITEC+LSRL ||  
 
|-
 
|-
−
| H4JYY8G || ?umSi, 1um SiO2, 0.7um Si undoped, 0.3um etch ||   || 1 || 1/4 || Numonyx/Intel ||  
+
|}
 +
{| border="3"
 +
|+ '''SOI patterned wafer table'''
 +
|- style="background:blue; color:white"
 +
! Wafer ID !! Substrate(um) !! BOX(um) !! Device layer (um) !! Details of device layer !! Rib Etch (um) !!# bought !! # remaining !! Supplier !! Note
 
|-
 
|-
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| HTJYYJG || ?umSi, 1um SiO2, 0.7um Si undoped, 0.4um etch ||   || 1 || 1 || Numonyx/Intel ||  
+
| H4JYY8G ||   || 1 || 0.7 || Undoped Si || 0.3 || 1 || 1/4 || umonyx/Intel || LASOR/PhASER
 +
|
 +
| H4JYY8G ||   || 1 || 0.7 || Undoped Si || 0.4 || 1 || 1 || umonyx/Intel || LASOR/PhASER
 
|-
 
|-
−
| HTJYULG || ?umSi, 1um SiO2, 0.7um Si undoped, 0.3um etch, Oxidation smoothed ||   || 1 || 1 || Numonyx/Intel ||  
+
| H4JYY8G ||   || 1 || 0.7 || Undoped Si || 0.3 || 1 || 1 || umonyx/Intel || LASOR/PhASER, oxidation smooth
 
|-
 
|-
−
|   ||   ||   ||   ||   ||   ||  
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|   ||   ||   ||   ||   ||   ||  ||  ||  ||  
 
|-
 
|-
 
|}
 
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|+ '''III/V wafer table'''
 
|+ '''III/V wafer table'''
 
|- style="background:red; color:white"
 
|- style="background:red; color:white"
−
! Wafer ID !! Layerstack !! Data and spec-sheet !! Number bought !! Number remaining !! Supplier !! Design/simulation results  
+
! Wafer ID !! Layerstack !! Data and spec-sheet !! # bought !! # remaining !! Supplier !! Design/simulation results  
 
|-  
 
|-  
 
| GLDA0908271-C ||   ||   || 5 || 3 || LandMark ||  
 
| GLDA0908271-C ||   ||   || 5 || 3 || LandMark ||  

Revision as of 16:41, 31 March 2010

SOI wafer table
Wafer ID Substrate(um) BOX(um) Device layer (um) Details of device layer # bought # remaining Supplier Note
1I29437.1 675 1 0.7 0.2um 1E14 B, 0.5um 1E10 21 18 SOITEC+LSRL  
1I29437.1 675 1 0.4 0.2um 1E14 B, 0.2um 1E10 4 0 SOITEC+LSRL  
SOI patterned wafer table
Wafer ID Substrate(um) BOX(um) Device layer (um) Details of device layer Rib Etch (um) # bought # remaining Supplier Note
H4JYY8G   1 0.7 Undoped Si 0.3 1 1/4 umonyx/Intel LASOR/PhASER H4JYY8G   1 0.7 Undoped Si 0.4 1 1 umonyx/Intel LASOR/PhASER
H4JYY8G   1 0.7 Undoped Si 0.3 1 1 umonyx/Intel LASOR/PhASER, oxidation smooth
                   
III/V wafer table
Wafer ID Layerstack Data and spec-sheet # bought # remaining Supplier Design/simulation results
GLDA0908271-C     5 3 LandMark  
             
             
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