Difference between revisions of "Wafer Table (old)"

Revision as of 12:11, 2 April 2010

**SOI wafer table**
Wafer ID	Substrate(um)	BOX(um)	Device layer (um)	Doped Si	Undoped Si	# bought	# remaining	Supplier
1I29437.1	675	1	0.7	0.2um 1E14 B	0.5um 1E10	21	18	SOITEC+LSRL
1I29437.1	675	1	0.4	0.2um 1E14 B	0.2um 1E10	4	0	SOITEC+LSRL
1H74447.1	675	1	0.7	0.3um 1E14 p type	0.4um 1E10	10	2+1/3+1/3	SOITEC
1H74447.1	675	1	0.6	0.3um 1E14 p type	0.6um 1E10	5	3	SOITEC
1H74447.1	675	1	0.55	0.3um 1E14 p type	0.25um 1E10	10	3	SOITEC
1G47090.1	675	1	1	0.3um 1E14 p type	0.7um 1E10	10	2	SOITEC
	675	3	1	0.25um 1E14 p type	0.75um 1E10	10	7+1/2+1/2	SOITEC

**SOI patterned wafer table**
Wafer ID	BOX(um)	Device layer (um)	Details of device layer	Rib Etch (um)	# bought	# remaining	Supplier	Note
H4JYY8G	1	0.7	Undoped Si	0.3	1	1/4	umonyx/Intel	LASOR/PhASER
H4JYY8G	1	0.7	Undoped Si	0.4	1	1	umonyx/Intel	LASOR/PhASER
H4JYY8G	1	0.7	Undoped Si	0.3	1	1	umonyx/Intel	LASOR/PhASER, oxidation smooth

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 {| border="3"
 |+ '''SOI wafer table'''
-|- style="background:red; color:white"
+|- style="background:green; color:white"
 ! Wafer ID !! Substrate(um) !! BOX(um) !! Device layer (um) !! Doped Si !! Undoped Si !! # bought !! # remaining !! Supplier !! Note
 |-
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 {| border="3"
 |+ '''III/V wafer table'''
-|- style="background:red; color:white"
+|- style="background:purple; color:white"
 ! Wafer ID !! Layerstack !! Data and spec-sheet !! # bought !! # remaining !! Supplier !! Design/simulation results
 |-