Revision as of 20:11, 19 January 2012

Agenda & Priority List

Back to Process Hybrid Silicon.

Priority list

• Process development:
  • Etch-back module (Jock, Jared)
  • Need to converge on process follower (Excel?) -> start with Si etch / VC etch / bonding
• III/V epi design
  • Finalize design
  • Order epi
• III/V SOA design
• III/V SOA mask design (UCSB-E-Phi-dev-2 @ UCSB E-Phi Runs)
  • Issue: Epi will arrive > 3 months -> test process follower with OPSIS run?
• SOI passives run fabrication

Issues brought up in meetings

13/01/2012

• Sudha/Yongbo.: should we undercut to define the current channel?

- (Martijn) high risk
- REFERENCE EPI: centered QW, similar to past epi + top etch-stop layer + InGaAsP contact helper(?)
- HIGH RISK EPI: e-block layers, GRINSCH

• Jon P.: Resist difficult to remove after Si-doping implants

- can remove with long strip, pirhana (hot)
- long-term: move to thin SiO2 underlayer (implant through this) and remove with BHF

• Jared H.: edge bead (may not be an issue, esp. for 4" wafer processing - use stayout of 5-10mm)

- for small samples, can surround with additional chips during spin

06/01/2012

• Jon P.: Resist nonuniformity for multiple-die exposure -> >= 1-cm stay-out area?
• Jock: Grating module works for etch depths < 120 nm
• Bandgap issue: PL peak is not equal to lasing wavelength, and lasing wavelength is not equal to SOA gain maximum
  • First have nice gain spectrum before we discuss further