Difference between revisions of "Hybrid Silicon Process Overview"

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(Optional process modules)
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! Process ID !! Process flow !! Process follower !! Description  
 
! Process ID !! Process flow !! Process follower !! Description  
 
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| WG etch ||   || [[media:WG Module.docx | Si WG etch‎]] || Rib waveguide formation, Alignment marks.
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| SOI Actives ||   || [[media:SOI_actives.docx | Si actives‎]] || Introduces diodes into the silicon layer
 
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| VC etch ||   || [[media:VC_module.docx | Si VC etch]] || Vertical channel etch
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| Protection layer ||   || [[media:protection.docx | protection layer]] || Use if die-bonding on only part of the chip - protects exposed Si
 
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| Bonding ||   || [[Media:Bonding short.docx‎ | Bonding]] || [[Media:Bonding process.docx‎ | Plasma assisted wafer bonding guide - Author:Michael D]]
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| Quantum Well Intermixing||   || [[Media:QWI.docx‎ | QWI]] || Changes the III-V bandgap in selected regions of the chip - useful for integrating multiple laser wavelengths and modulators with the same III-V epi
 
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| InP-mesa etch ||   || [[Media:RIE2 etch.docx‎ | P-mesa etch]] || Mesa etch to top SCH layer
 
| InP-mesa etch ||   || [[Media:RIE2 etch.docx‎ | P-mesa etch]] || Mesa etch to top SCH layer
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| N-metal deposition ||   || [[Media:n metal dep.docx‎ | N-metal deposition]] || N-metal (Ni/Ge/Au/Ni/Au)
 
| N-metal deposition ||   || [[Media:n metal dep.docx‎ | N-metal deposition]] || N-metal (Ni/Ge/Au/Ni/Au)
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| Ion implantation  ||   || [Media:ion implantation.docx‎ | Ion implantation] || Current channel definition by ion implantation
 
 
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| Oxide Planarization & Via formation ||   || [[Media:planarize and via etch.docx‎ | Planarization & Via etch]] || 1um oxide deposition & via etch
 
| Oxide Planarization & Via formation ||   || [[Media:planarize and via etch.docx‎ | Planarization & Via etch]] || 1um oxide deposition & via etch

Revision as of 09:23, 19 October 2012

Summary


The hybrid silicon process can be summarized as follows:
(1) Silicon-layer processing
Starting with an SOI (Silicon on Insulator) wafer, rib waveguides are patterned in the top silicon and vertical channels are etched to the buried oxide (the purpose of these vertical channels is to allow outgasing during bonding steps later in the process). Additional steps to introduce diodes into the silicon through doping are also possible, as are additional etch steps for gratings.
(2) III-V bonding and processing
III-V epi material is then die-bonded to the silicon and back-polished until a thin stack of III-V remains, after which wet etching removes the remainder of excess Indium Phosphide (there is typically a p-contact layer of InGaAs beneath this which acts as an etch stop). Gain elements are then patterned in the III-V by etching down through the epi stack roughly to the quantum wells (this patterned stack is then referred to as the "mesa"), a second etch step goes through the quantum wells to the n-InP, and finally the n-InP can be etched until the underlying silicon is exposed.
(3) Metallization
Thick p-contact metal is deposited on top of the mesa (although thin metal may already have been deposited for this purpose during the mesa definition). The mesa is then typically either subjected to a proton implantation step or an etch step to confine current to a narrow path directly beneath the p-contact. Metal for n-contacts is deposited, and a "buffer" layer (SU8, BCB, oxide, or some other dielectric) is added to allow metal traces to be overlaid on top of the waveguides without impacting the optical mode. Vias are etched through the buffer and "probe" metal (i.e. thick metal for probing and wirebonding) is deposited on top and patterned.

The actual process used to accomplish these steps is dependent on the project; in many of these steps there are a range of options available for processing. Below is a core process which should be considered the "template"; additional modules can be added to this as desired - these are provided below the core process along with a description of what they provide and their current status.

Core process

This is the core process which should be considered the "template"; additional modules can be added to this as desired.

Core Process Outline

Core process steps
Process ID Process flow Process follower Description
WG etch   Si WG etch‎ Rib waveguide formation, Alignment marks.
VC etch   Si VC etch Vertical channel etch
Bonding   Bonding Plasma assisted wafer bonding guide - Author:Michael D
InP-mesa etch   P-mesa etch Mesa etch to top SCH layer
QW wet etch   QW etch Active layer wet etch
N-metal deposition   N-metal deposition N-metal (Ni/Ge/Au/Ni/Au)
Buffer & Via formation   Planarization & Via etch 1um oxide deposition & via etch
P-/Probepad metal deposition   Probepad metallization P-/probepad metal stack (Pd/Ti/Pd/Au)


Optional process modules

These are process "modules" which can be selected as needed and added to the Core process (in some cases as alternatives to core process steps).
The established maturity (and therefore yield) of each module varies; add modules to suit individual applications, but be aware that each deviation from the core process introduces additional risk.

Optional process modules
Process ID Process flow Process follower Description
SOI Actives   Si actives‎ Introduces diodes into the silicon layer
Protection layer   protection layer Use if die-bonding on only part of the chip - protects exposed Si
Quantum Well Intermixing   QWI Changes the III-V bandgap in selected regions of the chip - useful for integrating multiple laser wavelengths and modulators with the same III-V epi
InP-mesa etch   P-mesa etch Mesa etch to top SCH layer
QW wet etch   QW etch Active layer wet etch
N-metal deposition   N-metal deposition N-metal (Ni/Ge/Au/Ni/Au)
Oxide Planarization & Via formation   Planarization & Via etch 1um oxide deposition & via etch
P-/Probepad metal deposition   Probepad metallization P-/probepad metal stack (Pd/Ti/Pd/Au)