Hybrid Silicon Process Overview
Summary
The hybrid silicon process can be summarized as follows:
(1) Silicon-layer processing
Starting with an SOI (Silicon on Insulator) wafer, rib waveguides are patterned in the top silicon and vertical channels are etched to the buried oxide (the purpose of these vertical channels is to allow outgasing during bonding steps later in the process). Additional steps to introduce diodes into the silicon through doping are also possible, as are additional etch steps for gratings.
(2) III-V bonding and processing
III-V epi material is then die-bonded to the silicon and back-polished until a thin stack of III-V remains, after which wet etching removes the remainder of excess Indium Phosphide (there is typically a p-contact layer of InGaAs beneath this which acts as an etch stop). Gain elements are then patterned in the III-V by etching down through the epi stack roughly to the quantum wells (this patterned stack is then referred to as the "mesa"), a second etch step goes through the quantum wells to the n-InP, and finally the n-InP can be etched until the underlying silicon is exposed.
(3) Metallization
Thick p-contact metal is deposited on top of the mesa (although thin metal may already have been deposited for this purpose during the mesa definition). The mesa is then typically either subjected to a proton implantation step or an etch step to confine current to a narrow path directly beneath the p-contact. Metal for n-contacts is deposited, and a "buffer" layer (SU8, BCB, oxide, or some other dielectric) is added to allow metal traces to be overlaid on top of the waveguides without impacting the optical mode. Vias are etched through the buffer and "probe" metal (i.e. thick metal for probing and wirebonding) is deposited on top and patterned.
The actual process used to accomplish these steps is dependent on the project; in many of these steps there are a range of options available for processing. Below is a core process which should be considered the "template"; additional modules can be added to this as desired - these are provided below the core process along with a description of what they provide and their current status.
Core process
This is the core process which should be considered the "template"; additional modules can be added to this as desired.
| Process ID | Process follower | Description |
|---|---|---|
| WG etch | File:WG Module.docx Si WG etch | Rib waveguide formation, Alignment marks. |
| VC etch | File:VC module.docx | Vertical channel etch |
| Bonding | File:Bonding short.docx | Plasma assisted wafer bonding guide - Author:Michael D |
| InP-mesa etch | File:RIE2 etch.docx | Mesa etch to top SCH layer |
| QW wet etch | File:QW wet etch.docx | Active layer wet etch |
| N-metal deposition | File:N metal dep.docx | N-metal (Ni/Ge/Au/Ni/Au) |
| Buffer & Via formation | File:Planarize and via etch.docx | 1um oxide deposition & via etch |
| P-/Probepad metal deposition | File:Probepad p-metal dep.docx | P-/probepad metal stack (Pd/Ti/Pd/Au) |
Optional process modules
These are process "modules" which can be selected as needed and added to the Core process (in some cases as alternatives to core process steps).
The established maturity (and therefore yield) of each module varies; add modules to suit individual applications, but be aware that each deviation from the core process introduces additional risk.
Status codes (Risk):
1 = established (can be dropped into the process with little first-order risk - this does not rule out risk from incompatibility with other modules)
2 = used frequently, but still subject to significant risks
3 = tested successfully at least once, but high risk
4 = not yet demonstrated at UCSB, expect considerable process development
| Process ID | Process follower | Description | Process Placement Rules | Status |
|---|---|---|---|---|
| SOI Actives | Si actives | Introduces diodes into the silicon layer | Must precede III-V bonding | 3 |
| SOI PDs | Si PDs | Renders diodes in the silicon layer into photodiodes | Back-end step (can be after probe metal); must be preceded by SOI Actives | 4 |
| Protection layer | protection layer | Protects exposed Si for selective die-bonding | immediately prior to III-V bonding (co-requires Gapfill/GFR modules) | 3 |
| Gapfill | Gapfill | adds protection in the "gap" between III-V die and protected Si | immediately post III-V bonding (co-requires Protection/GFR modules) | 3 |
| GF Removal (GFR) | GFR | removes protection layers and III-V in the "gap" | back-end step | 3 |
| Quantum Well Intermixing | QWI | Allows III-V bandgap adjustment in selected regions | add-on post-bond | 3 |
| Proton implantation | proton implantation | Defines current channel in the mesa by proton implantation | add after first thick metal dep (use thick metal as the channel mask) | 1 |
| N-InP definition | N-InP etch | Removes excess n-InP (reduces loss) | Add-on after n-metal deposition | 2 |
| SU8 Buffer | SU8 Buffer | SU8 polymer buffer (useful for high-speed rf) and vias | Replaces Core Buffer/Via step | 2 |
| Shallow gratings | Grating process | Shallow (<200nm) surface gratings in top Si | Add-on after VC step (can be combined with Deep gratings for double-depth features) | 1 |
| Deep gratings | Grating process | Deep (>200nm) surface gratings in top Si | Add-on after VC step (can be combined with Shallow gratings for double-depth features) | 2 |
Appendix
The old hybrid silicon page can be found [here.]
Additional information:
- Spreadsheet showing the modules used in various recent fabrication runs: HSP v 1.0.0
