Bluespec
SystemVerilog Documentation
Product Documentation
Tutorials
Examples
Papers
Labs
Training Slides
BSV
Product
Documentation
Bluespec
Reference Guide
The Bluespec Reference Guide is a detailed language reference manual
and set of documentation for the library packages.
Bluespec User
Guide
The Bluespec User Guide describes the mechanics and logistics of
running the Bluespec tools, using either the Bluespec development
workstation or the command line.
BSV
Quick Reference Card
This card is a short, convenient reference to Bluespec SystemVerilog
syntax.
Bluespec Style
Guide
This document is
provided as a supplemental aid to the Reference and User Guides.
It describes Bluespec SystemVerilog coding guidelines though a series
of descriptions and examples, where the objectives are to:
- bring experienced
Verilog and VHDL designers up to speed with the abilities and features
of Bluespec,
- enable designers
to produce expected RTL with respect to interfaces, and structures,
- allow
designers to take
advantage of the extensive libraries provided by Bluespec.
Known Problems
and Solutions (KPNS)
KPNS describes some known issues with the compiler and their solutions.
Verification
with Bluespec System Verilog
This document provides a verification methodology for use with Bluespec
System Verilog designs.
Sce-Mi
Co-Emulation with Bluespec System Verilog
This document describes Bluespec System Verilog support for a
Sce-Mi-like co-emulation methodology.
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Tutorials
Tutorials
are fully-described examples which provide an incremental design to
teach and explain aspects of programming in Bluespec System
Verilog. Tutorials are
contained in $BLUESPEC_HOME/training/BSV/tutorials.
Hello
World
This is Bluespec's hardware equivalent of a "Hello World!". If
you
want to get a feel for the steps in building your first design and
using the toolset, this is a great starter tutorial.
BSV
Hello World
Designing
a Counter
If you want to get a feel for building a simple design and testbench
using Bluespec's toolset and methodology, this is another great starter
tutorial. This is a
hands-on, progressive walk-through of a relatively small example.
BSV
101: Designing a Counter
Intelligent
Traffic Light System
This tutorial develops a Bluespec specification of an intelligent
traffic light at an intersection. It is a good review and
practice for those who have completed Bluespec training and can also be
used as an introduction to Bluespec.
The
use of rules is highlighted in this tutorial.
BSV
Traffic Light System
BSV: A Simple
Configuration Bus
This is an advanced tutorial for the user who has completed
Bluespec training. This tutorial examines a simplified
configuration bus example to explain the use of the Bluespec library
LBus package, which provides full-featured configuration bus
capability.
Module Context
Tutorial
This is an advanced tutorial for the user who has completed
Bluespec training. This tutorial describes a way to carry
additional state between modules in a hierarchy by using the
ModuleContext monad.
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BSV Examples
Here are more
complex examples using features of Bluespec SystemVerilog.
Examples are contained in $BLUESPEC_HOME/training/BSV/examples.
Vending
Machine
This
example implements a vending machine which accepts 10 cent and 50
cent coins as input. The
$BLUESPEC_HOME/training/BSV/examples/vending
directory contains a Vending.bsv file with the BSV code, and a
TestVending.bsv file which contains the testbench that drives it.
There is also a Vending.bspec project file for use with the development
workstation.
Design
by Refinement of an Interconnect
This
example takes a functionally correct, executable, synthesizable design
and refines it to greater levels of complexity. Each refinement
is a local change, which keeps the rest of the code intact. All
four versions are fully synthesizable. This directory includes
documentation and full BSV source code for all four versions, along
with the testbenches and project (.bspec) files for the development
workstation.
DMA
Controller
This
example starts with a simple 1 channel 1 bus DMA controller and refines
it to a 2 channel 2 port model, with pipelined and concurrent
transactions. This directory contains a presentation describing
the design, code for the original design (v0) and 4 refinements
(v1,v2,v3 and v4). Each version of the design has the full BSV
source code along with testbenches and expected results as well as
project (.bspec) files for use with the development workstation.
The DMA
controller files are found in
$BLUESPEC_HOME/training/BSV/examples/DMA_refinement.
A
Parameterized Model
of a Crossbar Switch
This
document outlines the design of a highly parameterized butterfly
switch design (crossbar switch). You’ll find this design to be both
succinctly written and fully synthesizable into a high-performance
implementation. This paper includes a description of the design
problem as well as the solution, including source code for the design
and testbench as well as a project (.bspec) file for use with the
development workstation.
Importing a Verilog SRAM into Bluespec SystemVerilog
This example consists of a set of files which demonstrate a simple
example of importing a Verilog SRAM into Bluespec SystemVerilog.
The directory contains a README.txt
file which describes the example files and how to use them. The
RAM example files are found in
$BLUESPEC_HOME/training/BSV/examples/RAMs.
TLM DMA
This example describes how to build a simple DMA using the AzureIP bus
fabric TLM library. The directory contains the BSV source code
along with a testbench and a presentation describing the example.
Also included is a project (.bspec) file for use with the development
workstation. The TLM DMA example files are found in
$BLUESPEC_HOME/training/BSV/examples/TLMDMA.
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BSV Papers
This
directory, $BLUESPEC_HOME/training/BSV/papers, contains papers of
interest
to the Bluespec SystemVerilog community.
Achieving Timing Closure with
Bluespec SystemVerilog
This paper descibes techniques used by the Bluespec SystemVerilog
designer to achieve timing closure.
Reliable Design with
Multiple
Clock Domains
This
paper presents a series of guiding principles for the management of
multiple clock domains in the design of Bluespec SystemVerilog.
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BSV
Labs
Provided
here are several sets of lab exercises to help you learn and review
Bluespec SystemVerilog. Each training course will usually include
a subset of these labs. The labs are contained in
$BLUESPEC_HOME/training/BSV/labs.
The Pipeline Lab
This lab will lead you through basic aspects of the Bluespec
SystemVerilog language and the usage of the Bluespec compiler, Bluesim
simulator and the Bluespec Development Workstation. There are 5
parts, each building on the previous part. In each part you will
find a description of the actual code you will have to generate and how
to use and invoke each of
the previously mentioned tools.
Elevator Lab
This lab will lead you through slightly more advanced topics of the
Bluespec System Verilog language and usage of the Bluespec compiler,
Bluesim simulator and the Bluespec Development Workstation. This
lab implements an elevator controls
system. There are 3
parts, each building on the previous part.
Multiple Clock Domain (MCD) Lab
In this lab you implement a FIFO switch, test the implementation and
then modify it to be a mult-clock domain switch. The text for the
lab is contained in the link above. The
$BLUESPEC_HOME/training/BSV/labs/MCD directory contains the lab files,
solutions and testbenches for the simple switch and the MCD version of
the switch.
Multiplier Labs
These labs lead you through implementing successively more complex
multiplier circuits. The document mult.pdf in the $BLUESPEC_HOME/training/BSV/labs/mult0
directory contains directions for all four labs using the development
workstation.
Mult0
In this lab
you review and compile a multiplier, which is already written and
contained in Mult0.bsv. The results can be viewed with different
simulators. Mult0 files are contained in the
$BLUESPEC_HOME/training/BSV/labs/mult0 directory.
Mult1
This is a
version of the multiplier lab with a separate testbench in which you
add methods and make other simple changes to the multiplier.
Mult1 files are contained in the $BLUESPEC_HOME/training/BSV/labs/mult1
directory.
Mult2
In this lab
you will implement a booth multiplier. Mult2 files are
contained in the $BLUESPEC_HOME/training/BSV/labs/mult2
directory.
Mult3
This is a
considerably more complicated design than any of the previous
multiplier labs, and uses some of BSV's more advanced features.
Using the results from Mult1 and Mult2, you will create a server farm
of multipliers. Some of the more advanced features used
are: passing arrays of interfaces as arguments, generating rules inside
of synthesis-time loops, multiple rules manipulating the same resource,
polymorphic modules, and use of provided library modules, such as
CompletionBuffer. Mult3 files are contained in the $BLUESPEC_HOME/training/BSV/labs/mult3
directory.
Fibonacci Circuit Labs
The following labs lead you through successively more complicated
versions of a Fibonacci circuit. The document fib.pdf in the $BLUESPEC_HOME/training/BSV/labs/fib1
directory contains directions for all three labs using the development
workstation.
Fibonacci Lab 1
In this lab
you implement a Fibonacci circuit based on a provided module
outline. You will then compile the circuit and view the results
with different simulators. Fib1 files are contained in the
$BLUESPEC_HOME/training/BSV/labs/fib1 directory.
Fibonacci Lab 2
This lab adds
interface methods to the Fibonacci circuit completed in Fib1.
Fib2 files are contained in the
$BLUESPEC_HOME/training/BSV/labs/fib2 directory.
Fibonacci Lab 3
In this
version the Fib interface is changed and the code implements a
double-issue Fibonacci circuit using FIFOs.
Fib3 files are contained in the
$BLUESPEC_HOME/training/BSV/labs/fib3 directory.
Direct-C Lab
This lab is composed of simple exercises to develop familiarity with
the Direct C feature in BSV.
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BSV
Training
Slides
The slides
constitue a complete, multi-day course to teach and learn Bluespec
SystemVerilog.
Lecture
1
Introduction
Lecture
8 Performance Tuning
Lecture
2 Combinational Structures and Basic Types
Lecture
9 More on Module Interfaces
Lecture
3
Types
Lecture
10
Multiple Clock Domains
Lecture
4 Module Hierarchy
Lecture
11 Compiling, Running, and Debugging
Lecture 5
Rules
Lecture 12
Conclusion
Lecture
6
Rule Scheduling
Lecture
13 Direct-C
Lecture
7 Modularizing Behavior with Interface Methods
Lecture
14 Using the Development Workstation
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