DesignRules
From OptoelectronicsWiki
Design Rules
WG
- 3 um trenches for 200 um S-bends keep bending losses minimal
- Put 50 um trench around Verniers and alignment markers
VC
- 8 um x 8 um, 50 um separation
- No VC around verniers, so verniers have a chance of being exposed after substrate removal
- Detailed design rule, particularly for dense waveguide array (e.g., spiral, AWG), see File:DesignRule VOC.pptx.
- Using L-Edit's DRC to make sure no VCs on waveguides
Mesa
- 14 um wide
QW
- 16 um wide
Thick p metal
- Same at N metal
- 4 um wide
- Keep 11 um separation between thick P and N metal.
N Metal
- 20 um wide
Implant
- 12 um wide
- Implant after anneal to ensure the quality
Via
- Min. 6 um opening
- Open up area that is uniform at bottom
Plating
- Use SPR series positive photoresist
Square/Circular TLM patterns design rules
- Distance between adjacent pads - 4 to 30 microns in 5 or more steps.
Smaller the distance, more accurate the estimate.
- Pad width/diameter must be atleast 2x the max distance between pads.
Eg. Say if you have 6 pads with 5,8,12,15,20 micron spacing, it is recommended that the pad be > (2x20) microns wide
- Rectangular/square pads will need to be etched on the outer sides for isolation. That is not the case with circular pads.
- With circular pads, it is difficult to lift-off small rings (<5 microns)
Keep radius between 30-60 microns.
- Also, it is good to have a set of PTLMs that will be exposed to implantation step. This would be a way to check if the
implantation was effective. Resistance between pads with implantation must be hundred or kilo ohms or larger.
First draft of document explaining these: File:DesignRules.xlsx
Processing Rules
Always put a dummy/witness sample in the chamber when depositing metals and dielectrics.
- Samples can later be used for determining thicknesses.
- These samples can also be used if a given layer has to be etched on the real sample, but etch is not well characterized.