Si/Ge PD
Contents
Overview
Gen 1: surface-normal PD
Design
Fabrication
Process flow: File:SiGePD v2 proc flow.pptx
Process follower: File:SiGePD v2 wcomments.xlsx
Results
Gen 2: waveguide PD
Design
Fabrication
Fabrication for the waveguide design is composed of two parts: pre-growth Si processing and post-growth processing. The pre-growth processing included n-implant and annealing steps. Since this had not been done by our group before, I did a brief experiment to ensure that the final doping would match the designed doping. A description of the experiment is below.
The full process flow is here: File:WGPD fullprocess.pptx
Tht process follower is here: File:WGPD Si v2.xlsx
General fabrication process development
Hardmask etching
The group standard SiOvert etch was not compatible with Ge substrates (it requires very high RIE powers), so I looked at alternative ICP etches using CF4 and CHF3 for SiO2 etching: File:Alternatives to SiOVert.pptx. I also looked at the SF6/Ar etch used by the Coldren and Rodwell groups, but the etch rate of Ge was very fast and there was a lot of undercut. I settled on Ben Curtin's CF4/CHF3 etch, and then added a chrome hardmask to make removing the photoresist easier. The chrome dep/patterning process is in the waveguide PD traveler, and comes directly from the Coldren group.
Vertical Ge (and Si) etching
ICP etches using Cl, CF4, and SF6 chemistries: File:Vertical Ge etching.pptx. The etch I finally ended up using is not very vertical for Ge, but it is very vertical for Si, so may be of interest to the rest of the group.
Selective removal of Ge
File:Selective Ge wet etching.pptx
N-implant verification
Phosphorous implant in Silicon: File:N-implant verification.pptx
