Difference between revisions of "HSP priority list"

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=Agenda & Priority List=
 
=Agenda & Priority List=
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 +
 +
Back to [[Process Hybrid Silicon]].
  
 
==Priority list==
 
==Priority list==
 
* Process development:
 
* Process development:
 
** Etch-back module (Jock, Jared)
 
** Etch-back module (Jock, Jared)
** Need to  
+
** Need to converge on process follower (Excel?) -> start with Si etch / VC etch / bonding
 
* III/V epi design
 
* III/V epi design
 
** Finalize design
 
** Finalize design
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* III/V SOA mask design (UCSB-E-Phi-dev-2 @ [[UCSB E-Phi Runs]])
 
* III/V SOA mask design (UCSB-E-Phi-dev-2 @ [[UCSB E-Phi Runs]])
 
** Issue: Epi will arrive > 3 months -> test process follower with OPSIS run?
 
** Issue: Epi will arrive > 3 months -> test process follower with OPSIS run?
 
+
* SOI passives run fabrication
  
 
==Issues brought up in meetings==
 
==Issues brought up in meetings==
===05/01/2012===
+
===04/20/2012===
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[[DUV Stepper development]]
 +
 
 +
===03/02/2012===
 +
*Sudha - Removal of organics(/polymer) after RIE#2 etch: Gasonics + 10sec HF etch + Gasonics.
 +
 
 +
*Bonding (Jon P.) - Could get some tips/demo from Aurrion:
 +
**PR while cleaving
 +
**Minimal handling
 +
 
 +
===20/01/2012===
 +
* AR (Sudha): Process follower to Jon P. & Martijn (incl. wafer details: who, where, version. etc.)
 +
* Epi order: 3 2" wafers per epi design, 2mm spacing between dies
 +
** The Epi of the standard landmark LD design with GRIN-SCH and 6 pairs of 5nm/9nm well/barrier has a low refractive index --> go to 7 pairs of 6nm/9nm well/barrier and revised GRIN-SCH for a higher refractive index.
 +
 
 +
===13/01/2012===
 +
* Sudha/Yongbo.: should we undercut to define the current channel?
 +
- (Martijn) high risk <br>
 +
- REFERENCE EPI:  centered QW, similar to past epi + top etch-stop layer + InGaAsP contact helper(?)<br>
 +
- HIGH RISK EPI: e-block layers, GRINSCH
 +
 
 +
* Jon P.: Resist difficult to remove after Si-doping implants
 +
- can remove with long strip, pirhana (hot) <br>
 +
- long-term:  move to thin SiO2 underlayer (implant through this) and remove with BHF
 +
* Jared H.:  edge bead (may not be an issue, esp. for 4" wafer processing - use stayout of 5-10mm)
 +
- for small samples, can surround with additional chips during spin
 +
 
 +
===06/01/2012===
 
* Jon P.: Resist nonuniformity for multiple-die exposure -> >= 1-cm stay-out area?
 
* Jon P.: Resist nonuniformity for multiple-die exposure -> >= 1-cm stay-out area?
 
* Jock: Grating module works for etch depths < 120 nm
 
* Jock: Grating module works for etch depths < 120 nm
 
* Bandgap issue: PL peak is not equal to lasing wavelength, and lasing wavelength is not equal to SOA gain maximum
 
* Bandgap issue: PL peak is not equal to lasing wavelength, and lasing wavelength is not equal to SOA gain maximum
 
** First have nice gain spectrum before we discuss further
 
** First have nice gain spectrum before we discuss further

Latest revision as of 14:48, 20 April 2012

Agenda & Priority List[edit]

Back to Process Hybrid Silicon.

Priority list[edit]

  • Process development:
    • Etch-back module (Jock, Jared)
    • Need to converge on process follower (Excel?) -> start with Si etch / VC etch / bonding
  • III/V epi design
    • Finalize design
    • Order epi
  • III/V SOA design
  • III/V SOA mask design (UCSB-E-Phi-dev-2 @ UCSB E-Phi Runs)
    • Issue: Epi will arrive > 3 months -> test process follower with OPSIS run?
  • SOI passives run fabrication

Issues brought up in meetings[edit]

04/20/2012[edit]

DUV Stepper development

03/02/2012[edit]

  • Sudha - Removal of organics(/polymer) after RIE#2 etch: Gasonics + 10sec HF etch + Gasonics.
  • Bonding (Jon P.) - Could get some tips/demo from Aurrion:
    • PR while cleaving
    • Minimal handling

20/01/2012[edit]

  • AR (Sudha): Process follower to Jon P. & Martijn (incl. wafer details: who, where, version. etc.)
  • Epi order: 3 2" wafers per epi design, 2mm spacing between dies
    • The Epi of the standard landmark LD design with GRIN-SCH and 6 pairs of 5nm/9nm well/barrier has a low refractive index --> go to 7 pairs of 6nm/9nm well/barrier and revised GRIN-SCH for a higher refractive index.

13/01/2012[edit]

  • Sudha/Yongbo.: should we undercut to define the current channel?

- (Martijn) high risk
- REFERENCE EPI: centered QW, similar to past epi + top etch-stop layer + InGaAsP contact helper(?)
- HIGH RISK EPI: e-block layers, GRINSCH

  • Jon P.: Resist difficult to remove after Si-doping implants

- can remove with long strip, pirhana (hot)
- long-term: move to thin SiO2 underlayer (implant through this) and remove with BHF

  • Jared H.: edge bead (may not be an issue, esp. for 4" wafer processing - use stayout of 5-10mm)

- for small samples, can surround with additional chips during spin

06/01/2012[edit]

  • Jon P.: Resist nonuniformity for multiple-die exposure -> >= 1-cm stay-out area?
  • Jock: Grating module works for etch depths < 120 nm
  • Bandgap issue: PL peak is not equal to lasing wavelength, and lasing wavelength is not equal to SOA gain maximum
    • First have nice gain spectrum before we discuss further