Difference between revisions of "Si/Ge PD"
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= General fabrication process development = | = General fabrication process development = | ||
| + | == Ge/Si hardmask etching == | ||
| + | ICP etches using CF4 and CHF3 for SiO2 etching: [[file:Alternatives_to_SiOVert.pptx]]. At the time, I was using SPR220-3 as a mask, but now I use 955-0.9, which seems to come off much more cleanly. | ||
== Vertical Ge etching== | == Vertical Ge etching== | ||
ICP etches using Cl, CF4, and SF6 chemistries: [[file: Vertical_Ge_etching.pptx]] | ICP etches using Cl, CF4, and SF6 chemistries: [[file: Vertical_Ge_etching.pptx]] | ||
== N-implant verification== | == N-implant verification== | ||
Phosphorous implant in Silicon: [[file:N-implant_verification.pptx]] | Phosphorous implant in Silicon: [[file:N-implant_verification.pptx]] | ||
Revision as of 14:38, 27 April 2012
Contents
Overview
Gen 1: surface-normal PD
Design
Fabrication
Process flow: File:SiGePD v2 proc flow.pptx
Process follower: File:SiGePD v2 wcomments.xlsx
Results
Gen 2: waveguide PD
Design
Fabrication
Fabrication for the waveguide design is composed of two parts: pre-growth Si processing and post-growth processing. The pre-growth processing included n-implant and annealing steps. Since this had not been done by our group before, I did a brief experiment to ensure that the final doping would match the designed doping. A description of the experiment is below.
The full process flow is here: File:WGPD fullprocess.pptx
Tht process follower is here: File:WGPD Si v2.xlsx
General fabrication process development
Ge/Si hardmask etching
ICP etches using CF4 and CHF3 for SiO2 etching: File:Alternatives to SiOVert.pptx. At the time, I was using SPR220-3 as a mask, but now I use 955-0.9, which seems to come off much more cleanly.
Vertical Ge etching
ICP etches using Cl, CF4, and SF6 chemistries: File:Vertical Ge etching.pptx
N-implant verification
Phosphorous implant in Silicon: File:N-implant verification.pptx
