Difference between revisions of "CaseList"

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{| border="3"
|+ '''Hybrid Silicon Process Modules'''
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|+ '''Hybrid Silicon Process'''
 
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|- style="background:red; color:white"
 
! Process Step!! Issue or Defect !!  Link                   
 
! Process Step!! Issue or Defect !!  Link                   
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| [[Dice and polish]] ||   ||   ||  
 
| [[Dice and polish]] ||   ||   ||  
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| [[Initial standard wafer testing]] ||   ||   ||  
 
 
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Revision as of 09:29, 3 November 2011

Process Issues and Defects

Hybrid Silicon Process
Process Step Issue or Defect Link
Initial wafer check      
Dice and cleave      
SOI waveguide      
SOI grating      
SOI actives      
Vertical channel      
Protection layer      
Quantum well intermixing      
Wafer bonding      
Gap fill      
P-mesa      
Lower SCH      
N-InP      
N-metal      
P-metal      
Ion implantation      
Via      
Probe metal      
Remove III/V in gap      
Dice and polish