Difference between revisions of "CaseList"

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(Typical Processing Issues and Solutions)
 
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| [[Dice and cleave]] ||   ||   ||  
 
| [[Dice and cleave]] ||   ||   ||  
 
|-
 
|-
| [[SOI waveguide definition]] ||   ||   ||  
+
| [[SOI waveguide]] ||   ||   ||  
 
|-
 
|-
| [[SOI grating definition]] ||   ||   ||  
+
| [[SOI grating]] ||   ||   ||  
 
|-
 
|-
| [[SOI actives definition]] ||   ||   ||  
+
| [[SOI actives]] ||   ||   ||  
 
|-
 
|-
| [[Vertical channel definition]] ||  ||   ||  
+
| [[Vertical channel]] ||  ||   ||  
 
|-
 
|-
| [[Protection layer definition]] ||   ||   ||  
+
| [[Protection layer]] ||   ||   ||  
 
|-
 
|-
 
| [[Quantum well intermixing]] ||   ||   ||  
 
| [[Quantum well intermixing]] ||   ||   ||  
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| [[Gap fill]] ||   ||   ||  
 
| [[Gap fill]] ||   ||   ||  
 
|-
 
|-
| [[P-mesa definition]] ||   ||   ||  
+
| [[P-mesa]] ||   ||   ||  
 
|-
 
|-
| [[Lower SCH definition]] ||  ||   ||  
+
| [[Lower SCH]] ||  ||   ||  
 
|-
 
|-
| [[N-InP definition]] ||   ||   ||  
+
| [[N-InP]] ||   ||   ||  
 
|-
 
|-
| [[N-metal definition]] ||   ||   ||  
+
| [[N-metal]] ||   ||   ||  
 
|-
 
|-
| [[P-metal definition]] ||   ||   ||  
+
| [[P-metal]] ||   ||   ||  
 
|-
 
|-
 
| [[Ion implantation]] ||   ||   ||  
 
| [[Ion implantation]] ||   ||   ||  
 
|-
 
|-
| [[Via definition]] ||   ||   ||  
+
| [[Via]] ||   ||   ||  
 
|-
 
|-
 
| [[Probe metal]] ||   ||   ||  
 
| [[Probe metal]] ||   ||   ||  

Revision as of 09:27, 3 November 2011

Process Issues and Defects

Hybrid Silicon Process Modules
Process Step Issue or Defect Link
Initial wafer check      
Dice and cleave      
SOI waveguide      
SOI grating      
SOI actives      
Vertical channel      
Protection layer      
Quantum well intermixing      
Wafer bonding      
Gap fill      
P-mesa      
Lower SCH      
N-InP      
N-metal      
P-metal      
Ion implantation      
Via      
Probe metal      
Remove III/V in gap      
Dice and polish      
Initial standard wafer testing