Difference between revisions of "Process Hybrid Silicon"

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|+ '''Hybrid Silicon Process Modules'''
 
|+ '''Hybrid Silicon Process Modules'''
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|- style="background:red; color:white"
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|- style="background:slategrey; color:white"
 
! Module !! Manager !! Status !! Description  
 
! Module !! Manager !! Status !! Description  
 
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| [[Dice and cleave]] || Jared || style="background:lime" |   ||  
 
| [[Dice and cleave]] || Jared || style="background:lime" |   ||  
 
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| [[SOI waveguide definition]] || Sudha || style="background:yellow" |   ||  
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| [[SOI waveguide definition]] || Sudha || style="background:orang" |   ||  
 
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| [[SOI grating definition]] || Jock || style="background:yellow" |   ||  
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| [[SOI grating definition]] || Jock || style="background:orange" |   ||  
 
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| [[SOI actives definition]] || Jon D. || style="background:red" |   ||  
 
| [[SOI actives definition]] || Jon D. || style="background:red" |   ||  
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| [[Vertical channel definition]] || Sudha || style="background:lime" |   ||  
 
| [[Vertical channel definition]] || Sudha || style="background:lime" |   ||  
 
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| [[Protection layer definition]] || Geza || style="background:yellow" |   ||  
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| [[Protection layer definition]] || Geza || style="background:orange" |   ||  
 
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| [[Quantum well intermixing]] || Sid || style="background:yellow" |   ||  
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| [[Quantum well intermixing]] || Sid || style="background:orange" |   ||  
 
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| [[Wafer bonding]] || Jon P., Di || style="background:yellow" |   ||  
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| [[Wafer bonding]] || Jon P., Di || style="background:orange" |   ||  
 
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| [[Gap fill]] || Geza || style="background:yellow" |   ||  
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| [[Gap fill]] || Geza || style="background:orange" |   ||  
 
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| [[P-mesa definition]] || Geza || style="background:yellow" |   ||  
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| [[P-mesa definition]] || Geza || style="background:orange" |   ||  
 
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| [[Lower SCH definition]] || Geza || style="background:yellow" |   ||  
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| [[Lower SCH definition]] || Geza || style="background:orange" |   ||  
 
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| [[N-InP definition]] || Geza || style="background:red" |   ||  
 
| [[N-InP definition]] || Geza || style="background:red" |   ||  
 
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| [[N-metal definition]] || Sid || style="background:yellow" |   ||  
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| [[N-metal definition]] || Sid || style="background:orange" |   ||  
 
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| [[P-metal definition]] || Jock, Sid || style="background:red" |   ||  
 
| [[P-metal definition]] || Jock, Sid || style="background:red" |   ||  
 
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| [[Ion implantation]] || Sid || style="background:yellow" |   ||  
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| [[Ion implantation]] || Sid || style="background:orange" |   ||  
 
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| [[Via definition]] || Jock || style="background:yellow" |   ||  
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| [[Via definition]] || Jock || style="background:orange" |   ||  
 
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|-
 
| [[Probe metal definition]] || Sid || style="background:lime" |   ||  
 
| [[Probe metal definition]] || Sid || style="background:lime" |   ||  
 
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|-
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| [[Remove III/V in gap]] || Geza || style="background:yellow" |   ||  
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| [[Remove III/V in gap]] || Geza || style="background:orange" |   ||  
 
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|-
 
| [[Dice and polish]] || Jared, Geza || style="background:lime" |   ||  
 
| [[Dice and polish]] || Jared, Geza || style="background:lime" |   ||  
 
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|-
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| [[Initial standard wafer testing]] || Martijn || style="background:lime" |   ||  
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| [[Initial standard wafer testing]] || Martijn || style="background:lime" | &nbsp; || Blabla <br> bla bla
 
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<span style="background:lime"> ___ </span>  Low risk: >95% yield, established process module; <br>
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<span style="background:orange"> ___ </span>  Medium risk: ~50% - 95% yield, relatively new process module or minor issues; <br>
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<span style="background:red"> ___ </span>  High risk: <50% yield, non-established process or major issues. <br>
  
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<br>
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<br>
  
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==Old process followers==
 
==Old process followers==

Revision as of 20:18, 10 November 2011

Standardized Process Follower

Hybrid Silicon Process Modules
Module Manager Status Description
Initial wafer check      
Dice and cleave Jared    
SOI waveguide definition Sudha    
SOI grating definition Jock    
SOI actives definition Jon D.    
Vertical channel definition Sudha    
Protection layer definition Geza    
Quantum well intermixing Sid    
Wafer bonding Jon P., Di    
Gap fill Geza    
P-mesa definition Geza    
Lower SCH definition Geza    
N-InP definition Geza    
N-metal definition Sid    
P-metal definition Jock, Sid    
Ion implantation Sid    
Via definition Jock    
Probe metal definition Sid    
Remove III/V in gap Geza    
Dice and polish Jared, Geza    
Initial standard wafer testing Martijn   Blabla
bla bla



___ Low risk: >95% yield, established process module;
___ Medium risk: ~50% - 95% yield, relatively new process module or minor issues;
___ High risk: <50% yield, non-established process or major issues.




Old process followers

Single steps of hybrid silicon processes
Process ID Version Process flow Process follower Description
SP-PWD   Si WG etch‎ Si WG etch‎ Single etch-step SOI process; passive components
SP-VC     Si VC etch Vertical channel etch
HSP-METCH     Mesa etch Forms mesa: see page for optimization efforts
HSP-QW     III-V QW etch Quantum well etch
HSP-NETCH     n-layer etch Remove n-layer to expose Si
HSP-PTLM     p-TLM step An additional process step is necessary to pattern p-TLM structures
HSP-METAL     thin metal Thin metal deposition
HSP-PP     Probe pad deposition Pattern and deposit probe metal
Wafer bonding     Bonding Beginner's guide to plasma assisted wafer bonding
Wafer bonding II     direct wafer bonding O2 plasma assisted wafer bonding (rev. 2008)
Non-planar wafer bonding     non-planar bonding Non-planar wafer bonding for bonding multiple epis to a single Si piece (see Jon Geske's thesis)
TLM only     TLM only Post-bond process for use with a TLM-only mask set


Full device run hybrid silicon processes
Process ID Version Process flow Process follower Description
PHASER 2 PHASER PHASER PHASER (SOAs, thermal phase tuning pads, MMIs) process flow. Alignment mark coordinates
Epump 2   process flow Epump 2 Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches.
Self-aligned rev. 2   process flow self rev. 2 Self-aligned process, starts after substrate removal, revised 2007. Contains PR spin speeds and exposure times for Stepper (6300)

Check the Device Run page for more process followers, mask layout files, etc.



Reall old versions of hybrid silicon processes
Process ID Version Process flow Process follower Description
PHASER 1   PHASER gen 1 PHASER (SOAs, thermal phase tuning pads, MMIs) process flow.
Epump 2   process flow Epump 2 Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches.
Si WG etch 1   WG etch ca. 2008 Si waveguide etch process
Si WG etch 2   WG etch Si waveguide etch process with gratings, PR reflow, and vertical channels
Retrieved from "https://web.ece.ucsb.edu/oewiki/index.php?title=Process_Hybrid_Silicon&oldid=1808"