Difference between revisions of "Process Hybrid Silicon"
From OptoelectronicsWiki
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|+ '''Hybrid Silicon Process Modules''' | |+ '''Hybrid Silicon Process Modules''' | ||
|- style="background:slategrey; color:white" | |- style="background:slategrey; color:white" | ||
− | ! Module !! Manager !! Status !! | + | ! Module !! Manager !! Status !! Issues !! Current action items |
|- | |- | ||
− | | [[Initial wafer check]] || || style="background:lime" | || | + | | [[Initial wafer check]] || || style="background:lime" | || || - Make a list of standard tests (TBD) |
|- | |- | ||
− | | [[Dice and cleave]] || Jared || style="background:lime" | || | + | | [[Dice and cleave]] || Jared || style="background:lime" | || || |
|- | |- | ||
− | | [[SOI waveguide definition]] || Sudha || style="background:orang" | || | + | | [[SOI waveguide definition]] || Sudha || style="background:orang" | || - Non-uniformity due to variations in mask thickness (width, profile) <br> - Linewidth reduction || - Fabricate samples with sputtered and thermal oxide hard mask (11/25/'11) <br> - Quantify width and etch depth variations (11/25/'11) <br> CEM tests (11/25/'11) |
|- | |- | ||
− | | [[SOI grating definition]] || Jock || style="background:orange" | || | + | | [[SOI grating definition]] || Jock || style="background:orange" | || Improve uniformity on grating etch depth from run to run || |
|- | |- | ||
− | | [[SOI actives definition]] || Jon D. || style="background:red" | || | + | | [[SOI actives definition]] || Jon D. || style="background:red" | || - Not tested || - Implantation/anneal for doping needs to be characterized <br> - Contact resistance <br> - Heavy ion implant for photodiodes characterization <br> - Test structures on upcoming SWEEPER run |
|- | |- | ||
− | | [[Vertical channel definition]] || Sudha || style="background:lime" | || | + | | [[Vertical channel definition]] || Sudha || style="background:lime" | || || |
|- | |- | ||
− | | [[Protection layer definition]] || Geza || style="background:orange" | || | + | | [[Protection layer definition]] || Geza || style="background:orange" | || || |
|- | |- | ||
− | | [[Quantum well intermixing]] || Sid || style="background:orange" | || | + | | [[Quantum well intermixing]] || Sid || style="background:orange" | || || |
|- | |- | ||
− | | [[Wafer bonding]] || Jon P., Di || style="background:orange" | || | + | | [[Wafer bonding]] || Jon P., Di || style="background:orange" | || - Edge delamination <br> Delamination around e.g. AWGs <br> Low bonding yield (<50%) || - Make list of tests <br> (11/18/'11) <br> - Design test mask (TBD) |
|- | |- | ||
− | | [[Gap fill]] || Geza || style="background:orange" | || | + | | [[Gap fill]] || Geza || style="background:orange" | || || |
|- | |- | ||
− | | [[P-mesa definition]] || Geza || style="background:orange" | || | + | | [[P-mesa definition]] || Geza || style="background:orange" | || || |
|- | |- | ||
− | | [[Lower SCH definition]] || Geza || style="background:orange" | || | + | | [[Lower SCH definition]] || Geza || style="background:orange" | || || |
|- | |- | ||
− | | [[N-InP definition]] || Geza || style="background:red" | || | + | | [[N-InP definition]] || Geza || style="background:red" | || || |
|- | |- | ||
− | | [[N-metal definition]] || Sid || style="background:orange" | || | + | | [[N-metal definition]] || Sid || style="background:orange" | || || |
|- | |- | ||
− | | [[P-metal definition]] || Jock, Sid || style="background:red" | || | + | | [[P-metal definition]] || Jock, Sid || style="background:red" | || - Planarization not tested <br> - Non-reproducible contact resistance || |
|- | |- | ||
− | | [[Ion implantation]] || Sid || style="background:orange" | || | + | | [[Ion implantation]] || Sid || style="background:orange" | || || |
|- | |- | ||
− | | [[Via definition]] || Jock || style="background:orange" | || | + | | [[Via definition]] || Jock || style="background:orange" | || || |
|- | |- | ||
− | | [[Probe metal definition]] || Sid || style="background:lime" | || | + | | [[Probe metal definition]] || Sid || style="background:lime" | || || |
|- | |- | ||
− | | [[Remove III/V in gap]] || Geza || style="background:orange" | || | + | | [[Remove III/V in gap]] || Geza || style="background:orange" | || || |
|- | |- | ||
− | | [[Dice and polish]] || Jared, Geza || style="background:lime" | || | + | | [[Dice and polish]] || Jared, Geza || style="background:lime" | || || |
|- | |- | ||
− | | [[Initial standard wafer testing]] || Martijn || style="background: | + | | [[Initial standard wafer testing]] || Martijn || style="background:red" | || - No standard set of test structures <br> - Non-uniform test structures || |
|- | |- | ||
|} | |} |
Revision as of 20:41, 10 November 2011
Standardized Process Follower
Module | Manager | Status | Issues | Current action items |
---|---|---|---|---|
Initial wafer check | - Make a list of standard tests (TBD) | |||
Dice and cleave | Jared | |||
SOI waveguide definition | Sudha | - Non-uniformity due to variations in mask thickness (width, profile) - Linewidth reduction |
- Fabricate samples with sputtered and thermal oxide hard mask (11/25/'11) - Quantify width and etch depth variations (11/25/'11) CEM tests (11/25/'11) | |
SOI grating definition | Jock | Improve uniformity on grating etch depth from run to run | ||
SOI actives definition | Jon D. | - Not tested | - Implantation/anneal for doping needs to be characterized - Contact resistance - Heavy ion implant for photodiodes characterization - Test structures on upcoming SWEEPER run | |
Vertical channel definition | Sudha | |||
Protection layer definition | Geza | |||
Quantum well intermixing | Sid | |||
Wafer bonding | Jon P., Di | - Edge delamination Delamination around e.g. AWGs Low bonding yield (<50%) |
- Make list of tests (11/18/'11) - Design test mask (TBD) | |
Gap fill | Geza | |||
P-mesa definition | Geza | |||
Lower SCH definition | Geza | |||
N-InP definition | Geza | |||
N-metal definition | Sid | |||
P-metal definition | Jock, Sid | - Planarization not tested - Non-reproducible contact resistance |
||
Ion implantation | Sid | |||
Via definition | Jock | |||
Probe metal definition | Sid | |||
Remove III/V in gap | Geza | |||
Dice and polish | Jared, Geza | |||
Initial standard wafer testing | Martijn | - No standard set of test structures - Non-uniform test structures |
___ Low risk: >95% yield, established process module;
___ Medium risk: ~50% - 95% yield, relatively new process module or minor issues;
___ High risk: <50% yield, non-established process or major issues.
Old process followers
Process ID | Version | Process flow | Process follower | Description |
---|---|---|---|---|
SP-PWD | Si WG etch | Si WG etch | Single etch-step SOI process; passive components | |
SP-VC | Si VC etch | Vertical channel etch | ||
HSP-METCH | Mesa etch | Forms mesa: see page for optimization efforts | ||
HSP-QW | III-V QW etch | Quantum well etch | ||
HSP-NETCH | n-layer etch | Remove n-layer to expose Si | ||
HSP-PTLM | p-TLM step | An additional process step is necessary to pattern p-TLM structures | ||
HSP-METAL | thin metal | Thin metal deposition | ||
HSP-PP | Probe pad deposition | Pattern and deposit probe metal | ||
Wafer bonding | Bonding | Beginner's guide to plasma assisted wafer bonding | ||
Wafer bonding II | direct wafer bonding | O2 plasma assisted wafer bonding (rev. 2008) | ||
Non-planar wafer bonding | non-planar bonding | Non-planar wafer bonding for bonding multiple epis to a single Si piece (see Jon Geske's thesis) | ||
TLM only | TLM only | Post-bond process for use with a TLM-only mask set |
Process ID | Version | Process flow | Process follower | Description |
---|---|---|---|---|
PHASER | 2 | PHASER | PHASER | PHASER (SOAs, thermal phase tuning pads, MMIs) process flow. Alignment mark coordinates |
Epump 2 | process flow | Epump 2 | Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches. | |
Self-aligned rev. 2 | process flow | self rev. 2 | Self-aligned process, starts after substrate removal, revised 2007. Contains PR spin speeds and exposure times for Stepper (6300) |
Check the Device Run page for more process followers, mask layout files, etc.
Process ID | Version | Process flow | Process follower | Description |
---|---|---|---|---|
PHASER | 1 | PHASER gen 1 | PHASER (SOAs, thermal phase tuning pads, MMIs) process flow. | |
Epump 2 | process flow | Epump 2 | Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches. | |
Si WG etch | 1 | WG etch | ca. 2008 Si waveguide etch process | |
Si WG etch | 2 | WG etch | Si waveguide etch process with gratings, PR reflow, and vertical channels |