Process Hybrid Silicon

Standardized Process Follower

Hybrid Silicon Process Modules

Module	Manager	Status	Issues	Current action items
Initial wafer check				- Make a list of standard tests (TBD)
Dice and cleave	Jared
SOI waveguide definition	Sudha		- Non-uniformity due to variations in mask thickness (width, profile) - Linewidth reduction	- Fabricate samples with sputtered and thermal oxide hard mask (11/25/'11) - Quantify width and etch depth variations (11/25/'11) - CEM tests (11/25/'11)
SOI grating definition	Jock		- Improve uniformity on grating etch depth from run to run	- None yet; keep calibration run
SOI actives definition	Jon D.		- Not tested - Implantation/anneal for doping needs to be characterized - Contact resistance - Heavy ion implant for photodiodes characterization	- Test structures on upcoming SWEEPER run (est. 01/01/'12)
Vertical channel definition	Sudha
Protection layer definition	Geza		- III-V delamination at edge - Some III/V remains in gap	- Quantify amount of delamination (11/11/'11) - Test more aggressive III/V removal chemistry (12/02/'11)
Quantum well intermixing	Sid		- New process, current research	- Intel QWI project timeline
Wafer bonding	Jon P., Di		- Edge delamination - Delamination around e.g. AWGs - Low bonding yield (<50%)	- Make list of tests and test structures (11/18/'11) - Design test mask (Martijn, Di; TBD)
Gap fill	Geza
P-mesa definition	Geza		- Rough sidewalls, residues, uniformity	- Measure etch uniformity across taper test sample (11/111/'11) - Measure Si loss after n-InP etch (11/25/'11)
Lower SCH definition	Geza		- idem	- idem
N-InP definition	Geza		- idem	- idem
N-metal definition	Sid		- Non-reproducible contact resistance	- Test: Ti/Pt, Pd/Ti and Pd/Ge on p-InGaAs - Test: Pd/Ge and Ni/Ge/Au on n-InP - Sequential annealing and resistance measurement (TBD, 2 weeks total after start) - Design epi for improvement and test (TBD) - Make list of potential epi improvements (11/11/'11)
P-metal definition	Jock, Sid		- Planarization not tested - Non-reproducible contact resistance
Ion implantation	Sid		- Do we know the exact implant profile?
Via definition	Jock
Probe metal definition	Sid		- Open circuit through via - Check sticking with new planarization process	- Find cause and solution
Remove III/V in gap	Geza
Dice and polish	Jared, Geza
Initial standard wafer testing	Martijn		- No standard set of test structures - Non-uniform test structures

___ Low risk: >95% yield, established process module;
___ Medium risk: ~50% - 95% yield, relatively new process module or minor issues;
___ High risk: <50% yield, non-established process or major issues.

Old process followers

Single steps of hybrid silicon processes

Process ID	Version	Process flow	Process follower	Description
SP-PWD		Si WG etch‎	Si WG etch‎	Single etch-step SOI process; passive components
SP-VC			Si VC etch	Vertical channel etch
HSP-METCH			Mesa etch	Forms mesa: see page for optimization efforts
HSP-QW			III-V QW etch	Quantum well etch
HSP-NETCH			n-layer etch	Remove n-layer to expose Si
HSP-PTLM			p-TLM step	An additional process step is necessary to pattern p-TLM structures
HSP-METAL			thin metal	Thin metal deposition
HSP-PP			Probe pad deposition	Pattern and deposit probe metal
Wafer bonding			Bonding	Beginner's guide to plasma assisted wafer bonding
Wafer bonding II			direct wafer bonding	O2 plasma assisted wafer bonding (rev. 2008)
Non-planar wafer bonding			non-planar bonding	Non-planar wafer bonding for bonding multiple epis to a single Si piece (see Jon Geske's thesis)
TLM only			TLM only	Post-bond process for use with a TLM-only mask set

Full device run hybrid silicon processes

Process ID	Version	Process flow	Process follower	Description
PHASER	2	PHASER	PHASER	PHASER (SOAs, thermal phase tuning pads, MMIs) process flow. Alignment mark coordinates
Epump 2		process flow	Epump 2	Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches.
Self-aligned rev. 2		process flow	self rev. 2	Self-aligned process, starts after substrate removal, revised 2007. Contains PR spin speeds and exposure times for Stepper (6300)

Check the Device Run page for more process followers, mask layout files, etc.

Reall old versions of hybrid silicon processes

Process ID	Version	Process flow	Process follower	Description
PHASER	1		PHASER gen 1	PHASER (SOAs, thermal phase tuning pads, MMIs) process flow.
Epump 2		process flow	Epump 2	Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches.
Si WG etch	1		WG etch	ca. 2008 Si waveguide etch process
Si WG etch	2		WG etch	Si waveguide etch process with gratings, PR reflow, and vertical channels