Difference between revisions of "Process Hybrid Silicon"

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==Standardized Process Follower==
 
==Standardized Process Follower==
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[[media:Hybrid Silicon Process Follower - v1.2.xlsx|Hybrid Silicon Process Follower - v1.2.xlsx]]
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[[file:Hybrid Silicon Process Follower - v1.2.xlsx|Hybrid Silicon Process Follower - v1.2.xlsx]]
  
 
{| border="3"
 
{| border="3"
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| [[Gap fill]] || Geza || style="background:orange" |   ||   ||  
 
| [[Gap fill]] || Geza || style="background:orange" |   ||   ||  
 
|-
 
|-
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| [[P-mesa definition]] || Geza || style="background:orange" | &nbsp; || - Rough sidewalls, residues, uniformity || - Measure etch uniformity across taper test sample (11/111/'11) <br> - Measure Si loss before and after n-InP etch (01/2012) <br> - Measure etch depth of standard RIE2 (+ wet etch?) using p-cladding-InP (01/2012)
+
| [[P-mesa definition]] || Mike || style="background:orange" | &nbsp; || - Expect to move to SiO2 masks <br> - Cause of grass never determined || - Test SiO2 hardmask on P-mesa etch <br> - Continue scrubbing electrode and running 1 chip at a time to elude grass
 
|-
 
|-
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| [[Lower SCH definition]] || Geza || style="background:orange" | &nbsp; || - idem || - idem
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| [[Lower SCH definition]] || Mike || style="background:lime" | &nbsp; || - No existing issues || - idem
 
|-
 
|-
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| [[N-InP definition]] || Geza, Daryl || style="background:red" | &nbsp; || - Si waveguides attacked during etch || - idem
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| [[N-InP definition]] || Mike || style="background:orange" | &nbsp; || - Si waveguides loss increased marginally || - idem
 
|-
 
|-
 
| [[N-metal definition]] || Sid || style="background:orange" | &nbsp; || - Non-reproducible contact resistance || - Test: Ti/Pt, Pd/Ti and Pd/Ge on p-InGaAs <br> - Test: Pd/Ge and Ni/Ge/Au on n-InP <br> - Sequential annealing and resistance measurement (TBD, 2 weeks total after start) <br> - Design epi for improvement and test (TBD) <br> - Make list of potential epi improvements (11/11/'11)
 
| [[N-metal definition]] || Sid || style="background:orange" | &nbsp; || - Non-reproducible contact resistance || - Test: Ti/Pt, Pd/Ti and Pd/Ge on p-InGaAs <br> - Test: Pd/Ge and Ni/Ge/Au on n-InP <br> - Sequential annealing and resistance measurement (TBD, 2 weeks total after start) <br> - Design epi for improvement and test (TBD) <br> - Make list of potential epi improvements (11/11/'11)
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<br>
  
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==Old process followers==
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==EPHI Shuttle run-1 (SOA only)==
  
 +
[[media:Process follower.docx | Complete Process Follower]]
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{| border="3"
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|+ '''Modules for Process A - Lead Process'''
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|- style="background:red; color:white"
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! Process ID !! Process flow !! Process follower !! Description
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|-
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| WG etch || [[media:Dev-2.2_process_flows.pptx‎ | Complete Flow A‎]] || [[media:WG Module.docx | Si WG etch‎]] || Rib waveguide formation, Alignment marks.
 +
|-
 +
| VC etch || &nbsp; || [[media:VC_module.docx | Si VC etch]] || Vertical channel etch
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|-
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| Bonding || &nbsp; || [[Media:Bonding short.docx‎ | Bonding]] || [[Media:Bonding process.docx‎ | Plasma assisted wafer bonding guide - Author:Michael D]]
 +
|-
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| InP-mesa etch || &nbsp; || [[Media:RIE2 etch.docx‎ | P-mesa etch]] || Mesa etch to top SCH layer
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|-
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| QW wet etch || &nbsp; || [[Media:QW wet etch.docx‎ | QW etch]] || Active layer wet etch
 +
|-
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| N-metal deposition || &nbsp; || [[Media:n metal dep.docx‎ | N-metal deposition]] || N-metal (Ni/Ge/Au/Ni/Au)
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|-
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| Oxide Planarization & Via formation || &nbsp; || [[Media:planarize and via etch.docx‎ | Planarization & Via etch]] || 1um oxide deposition & via etch
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|-
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| P-/Probepad metal deposition  || &nbsp; || [[Media:Probepad p-metal dep.docx‎ | Probepad metallization]] || P-/probepad metal stack (Pd/Ti/Pd/Au)
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|-
  
 +
|}
 +
[[media:Process follower.docx | Complete Process Follower]]
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{| border="3"
 +
|+ '''Modules for Process B- Catch-up Process'''
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|- style="background:red; color:white"
 +
! Process ID !! Process flow !! Process follower !! Description
 +
|-
 +
| WG etch || [[media:Dev-2.2_process_flows.pptx‎ | Complete Flow‎ B]] || [[media:WG Module.docx | Si WG etch‎]] || Rib waveguide formation, Alignment marks.
 +
|-
 +
| VC etch || &nbsp; || [[media:VC_module.docx | Si VC etch]] || Vertical channel etch
 +
|-
 +
| Bonding || &nbsp; || [[Media:Bonding short.docx‎ | Bonding]] || [[Media:Bonding process.docx‎ | Plasma assisted wafer bonding guide - Author:Michael D]]
 +
|-
 +
| P-metal deposition  || &nbsp; || [[media:p metal deposition.docx | p-metal deposition]] || P-metal stack (Pd/W)
 +
|-
 +
| InP-mesa etch || &nbsp; || [[Media:RIE2 etch.docx‎ | P-mesa etch]] || Mesa etch to top SCH layer
 +
|-
 +
| QW wet etch || &nbsp; || [[Media:QW wet etch.docx‎ | QW etch]] || Active layer wet etch
 +
|-
 +
| N-metal deposition || &nbsp; || [[Media:n metal dep.docx‎ | N-metal deposition]] || N-metal (Ni/Ge/Au/Ni/Au)
 +
|-
 +
| Oxide Planarization & Via formation || &nbsp; || [[Media:planarize and via etch.docx‎ | Planarization & Via etch]] || 1um oxide deposition & via etch
 +
|-
 +
| Probepad metal deposition  || &nbsp; || [[Media:Probepad p-metal dep.docx‎ | Probepad metallization]] || Probepad metal stack (Pd/Ti/Pd/Au)
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|-
  
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|}
  
 +
==Old process followers==
  
  

Latest revision as of 17:27, 2 October 2012

Process Development Meeting[edit]

Agenda & List of Priorities


Standardized Process Follower[edit]

File:Hybrid Silicon Process Follower - v1.2.xlsx

Hybrid Silicon Process Modules
Module Manager Status Issues Current action items
Epitaxy layer design Sid, Yongbo   - No well-developed design method (tools, softwares?)
- No reliable quick-verification method 		- Survey on EPI designs from growers, literature and other groups
Initial wafer check Jon P., Martijn   - No standard set of test structures
- Non-uniform test structures 		- Make a list of standard tests (TBD)
Dice and cleave Jared B      
SOI waveguide definition Sudha   - Non-uniformity due to variations in mask thickness (width, profile)
- Linewidth reduction 		- Fabricate samples with sputtered and thermal oxide hard mask (11/25/'11)
- Quantify width and etch depth variations (11/25/'11)
- CEM tests (11/25/'11)
- Mask info: UCSB E-Phi Runs
SOI grating definition Jock   - Improve uniformity on grating etch depth from run to run - None yet; keep calibration run
SOI actives definition Jon D.   - Not tested
- Implantation/anneal for doping needs to be characterized
- Contact resistance
- Heavy ion implant for photodiodes characterization 		- Test structures on upcoming SWEEPER run (est. 01/02/'12)
Vertical channel definition Sudha     - Test mask: ideas due 12/14, mask review 12/20
- Mask info: UCSB E-Phi Runs;
Protection layer definition Geza   - III-V delamination at edge
- Some III/V remains in gap 		- Quantify amount of delamination (11/11/'11)
- Test more aggressive III/V removal chemistry (12/02/'11)
Quantum well intermixing Sid   - New process, current research - Intel QWI project timeline
Wafer bonding Jon P., Di   - Edge delamination
- Delamination around e.g. AWGs
- Low bonding yield (<50%) 		- Make list of tests and test structures (11/18/'11)
- Design test mask, info: UCSB E-Phi Runs
Gap fill Geza      
P-mesa definition Mike   - Expect to move to SiO2 masks
- Cause of grass never determined 		- Test SiO2 hardmask on P-mesa etch
- Continue scrubbing electrode and running 1 chip at a time to elude grass
Lower SCH definition Mike   - No existing issues - idem
N-InP definition Mike   - Si waveguides loss increased marginally - idem
N-metal definition Sid   - Non-reproducible contact resistance - Test: Ti/Pt, Pd/Ti and Pd/Ge on p-InGaAs
- Test: Pd/Ge and Ni/Ge/Au on n-InP
- Sequential annealing and resistance measurement (TBD, 2 weeks total after start)
- Design epi for improvement and test (TBD)
- Make list of potential epi improvements (11/11/'11)
P-metal definition Jock, Sid   - Planarization not tested
- Non-reproducible contact resistance 		- Test with PULSAR taper mask (TBD)
- Test BCB and SOG (12/09/'11)
Ion implantation Sid   - Do we know the exact implant profile?
- When should we implant?		  
Via definition Jock      
Probe metal definition Sid   - Open circuit through via
- Check sticking with new planarization process 		- Find cause and solution
Remove III/V in gap Geza, Daryl      
Dice and polish Jared(Dice), Geza      



___ Low risk: >95% yield, established process module;
___ Medium risk: ~50% - 95% yield, relatively new process module or minor issues;
___ High risk: <50% yield, non-established process or major issues.



EPHI Shuttle run-1 (SOA only)[edit]

Complete Process Follower

Modules for Process A - Lead Process
Process ID Process flow Process follower Description
WG etch Complete Flow A‎ Si WG etch‎ Rib waveguide formation, Alignment marks.
VC etch   Si VC etch Vertical channel etch
Bonding   Bonding Plasma assisted wafer bonding guide - Author:Michael D
InP-mesa etch   P-mesa etch Mesa etch to top SCH layer
QW wet etch   QW etch Active layer wet etch
N-metal deposition   N-metal deposition N-metal (Ni/Ge/Au/Ni/Au)
Oxide Planarization & Via formation   Planarization & Via etch 1um oxide deposition & via etch
P-/Probepad metal deposition   Probepad metallization P-/probepad metal stack (Pd/Ti/Pd/Au)

Complete Process Follower

Modules for Process B- Catch-up Process
Process ID Process flow Process follower Description
WG etch Complete Flow‎ B Si WG etch‎ Rib waveguide formation, Alignment marks.
VC etch   Si VC etch Vertical channel etch
Bonding   Bonding Plasma assisted wafer bonding guide - Author:Michael D
P-metal deposition   p-metal deposition P-metal stack (Pd/W)
InP-mesa etch   P-mesa etch Mesa etch to top SCH layer
QW wet etch   QW etch Active layer wet etch
N-metal deposition   N-metal deposition N-metal (Ni/Ge/Au/Ni/Au)
Oxide Planarization & Via formation   Planarization & Via etch 1um oxide deposition & via etch
Probepad metal deposition   Probepad metallization Probepad metal stack (Pd/Ti/Pd/Au)

Old process followers[edit]

Single steps of hybrid silicon processes
Process ID Version Process flow Process follower Description
SP-PWD   Si WG etch‎ Si WG etch‎ Single etch-step SOI process; passive components
SP-VC     Si VC etch Vertical channel etch
HSP-METCH     Mesa etch Forms mesa: see page for optimization efforts
HSP-QW     III-V QW etch Quantum well etch
HSP-NETCH     n-layer etch Remove n-layer to expose Si
HSP-PTLM     p-TLM step An additional process step is necessary to pattern p-TLM structures
HSP-METAL     thin metal Thin metal deposition
HSP-PP     Probe pad deposition Pattern and deposit probe metal
Wafer bonding     Bonding Beginner's guide to plasma assisted wafer bonding
Wafer bonding II     direct wafer bonding O2 plasma assisted wafer bonding (rev. 2008)
Non-planar wafer bonding     non-planar bonding Non-planar wafer bonding for bonding multiple epis to a single Si piece (see Jon Geske's thesis)
TLM only     TLM only Post-bond process for use with a TLM-only mask set


Full device run hybrid silicon processes
Process ID Version Process flow Process follower Description
PHASER 2 PHASER PHASER PHASER (SOAs, thermal phase tuning pads, MMIs) process flow. Alignment mark coordinates
Epump 2   process flow Epump 2 Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches.
Self-aligned rev. 2   process flow self rev. 2 Self-aligned process, starts after substrate removal, revised 2007. Contains PR spin speeds and exposure times for Stepper (6300)

Check the Device Run page for more process followers, mask layout files, etc.



Reall old versions of hybrid silicon processes
Process ID Version Process flow Process follower Description
PHASER 1   PHASER gen 1 PHASER (SOAs, thermal phase tuning pads, MMIs) process flow.
Epump 2   process flow Epump 2 Mostly designed for lasers, revised 4/6/07. Starts after WG and VC etches.
Si WG etch 1   WG etch ca. 2008 Si waveguide etch process
Si WG etch 2   WG etch Si waveguide etch process with gratings, PR reflow, and vertical channels
Retrieved from "https://web.ece.ucsb.edu/oewiki/index.php?title=Process_Hybrid_Silicon&oldid=3000"