Winter 2026: ECE137A
For students wishing to enroll in ece137A for winter 2027, please note the following:
1) Apparently to make sure that
there are sufficient enrollment slots set aside for soon-to-graduate seniors,
the department and the university-wide admissions office will often at least
initially deny registration to the class by students other than graduating
seniors. For the past several years I have found that
a very large number of students find themselves initially put on the wait
list. Please do not assume that this
means that you will be unable to take the class. The initial enrollment caps
placed by the university on this class are far far
below the number of students the class can accommodate. In the past 10 years,
for students who have taken the necessary prerequisites, I have never had a
case of a student denied registration to this class because of the class being
full. So, Please be patient, and work with me and the student office to get you
involved in this class.
The lecture room that is
normally assigned to this class can accommodate as many as 77 students. With
regard to the lab sessions, the lab can accommodate up to about 65 students, and the hours of the lab sessions
are meaningless: you work in the lab independently at whatever hours suit your schedule. So, it makes no
sense to restrict enrollment to 40 students.
So, if you are being told you
cannot register because either the lecture or the lab sessions are "full
up", please contact me by email. Please also fill out this link to apply to add the class.
2) If you have not taken all the necessary prerequisites, it is very important that you fill in this link to apply to add the class. After you complete the form, the student office will refer your application to me for me to review your background.
DO NOT GO TO THE SCHEDULED LAB HOURS during the first week of classes. The laboratory/design content of the class is run on an independent basis. Design projects are assigned and a due date is given. Students work in the lab constructing and testing their designs, working in the lab at whatever time they find most suitable to work.
Last updated 5/21/2026
Please hit the "Refresh" button to see recent updates to assignments,
etc.
Please also hit
"refresh" when viewing pdf files (lecture notes, assignments, etc.)
recent changes:
Final
exam review: Phelps 1437 Friday 3/13
from 4-5PM
Final
Exam:
Thursday
March 19, 12 - 3 p.m.
Location
if your last name starts with A through H: Phelps 1431
Location
if your last name starts with J through Z PSYCH 1902
Picking
Up Your Graded Assignments
***********************************************************************
Prof. Mark Rodwell
Office Hrs: Mondays, Wednesdays, Thursdays 4-5PM, ESB Room 2205F.
(tentative….we will change these times if they conflict with student class
schedules)
Mondays and Wednesdays, 11:00am - 12:15pm, PSYCH 1902
Mid-term Exam: Wednesday February 4 class period (same room as lecture)
Dead week: March 9-13
Last Lecture: March 11
Final Exam:
Thursday
March 19, 12 - 3 p.m.
Location
if your last name starts with A through H: Phelps 1431
Location if your last name starts with J through Z PSYCH 1902
(same room as lecture)
Please see
https://registrar.sa.ucsb.edu/calendars/academic-calendars and
https://registrar.sa.ucsb.edu/calendars/final-exams
There are evening reviews near the times of the 3 labs, and the final exam.
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Date |
Time |
Location |
Subject / Objective |
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Jan 23 |
5-6 PM |
Phelps 1437 |
lab 1 discussion |
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Feb 6 |
5-6 PM |
Phelps 1437 |
lab 2 discussion |
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Feb 27 |
5-6 PM |
Phelps 1437 |
lab 3 discussion |
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March 13 |
4-5 PM |
Phelps 1437 |
final review |
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TA |
Email |
office hours |
Location |
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Wonsik Oh |
wonsik@ucsb.edu |
T, 1-2PM |
TA trailer. |
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Yihao Wu |
yihao_wu@umail.ucsb.edu |
M, 3-4PM |
TA trailer |
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Adharsh Kumar Navarasu |
anavarasu@umail.ucsb.edu |
W 3-4 |
TA trailer |
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Please note that these office hours
will be replaced (will not be held ) during weeks when the TAs are holding
office hours in the lab. |
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Comments about class preparation.
The laboratory/design content of the class is run on an independent basis. Design projects are assigned and a due date is given. Students work in the lab, working in groups of two (not three or more) constructing and testing their designs, working in the lab at whatever time they find most suitable to work.
During the week of that each lab project is due, and the week prior to this, the above TA hours will *not* be held. Instead, the TAs will be in the lab to provide you with guidance in the lab, at hours posted both here and on the lab door.
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Dates and times when TA
hours will be held in the lab. Checkoff times=* |
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Sun: |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
Sat |
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Jan 19 |
Jan 20 |
Jan 21 |
Jan 22 |
Jan 23 |
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Jan 26 6-7: AN |
Jan 27 5-6: WO 6-7: AN |
Jan 28 5-630: WO 630-8: AN |
Jan 29 5-630: WO 630-8: AN |
Jan 30 checkoffs 6hrs: WO 6hrs: AN |
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Feb 9: |
Feb 10 1-2 WO |
Feb 11 3-4 AN |
Feb 12 3-4 YW, |
Feb 13 |
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Feb 16 |
Feb 17 4-645: WO |
Feb 18 4-6: WO |
Feb 19 5-615: WO 616-730: AN |
Feb 20 checkoffs 6hrs: WO 6hrs: AN |
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Feb 23 |
Feb 24 WO 6-7pm |
Feb 25 YW 4-5pm |
Feb 26 |
Feb 27 |
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March 2 |
March 3 7-830: WO |
March 4 8-10: WO |
March 5 8-10: WO 6-8: AN |
March 6 checkoffs 6hrs: WO 6hrs: AN |
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March 9 |
March 10 |
March 11 |
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Checkoffs will be in the lab, and will be by appointment. A signup sheet for lab checkoffs will be distributed by the TAs. Please see the TAs if you must change your appointment time. During the checkoff periods, the TAs are not available to provide you with guidance, and the lab is will be closed except to those checking off.
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Problem sets are due 11:59PM by upload to the class administration web page. |
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# |
week |
what |
due |
files |
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1 |
2 |
transistor bias circuits |
1/14/26 |
assignment: ece137a_ps1_2026.pdf |
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updates: |
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2 |
3 |
common-source &
common-emitter stages |
1/21/26 |
assignment: ece137a_ps2_2026.pdf |
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updates: |
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3 |
4 |
source/emitter
degeneration, common-gate/base stages |
1/28/26 |
assignment: ece137a_ps3_2026.pdf |
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updates: |
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4 |
6 |
followers, differential
stages |
2/11/26 |
assignment: ece137a_ps4_2026.pdf |
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updates: |
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5 |
7 |
multi-stage amplifiers |
2/18/26 |
assignment: ece137a_ps5_2026.pdf |
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updates: |
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6 |
8 |
multi-stage amplifiers |
2/25/26 |
assignment: ece137a_ps6_2026.pdf |
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updates: |
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7 |
9 |
multi-stage amplifier,
frequency response |
3/4/26 |
assignment: ece137a_ps7_2026.pdf |
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updates: |
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8 |
10 |
frequency response,
negative feedback |
not due; re-commended study problems |
assignment: ece137a_ps8_2026.pdf |
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updates: |
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Missing parameters in assignments: Often a problem statement will omit to give certain parameter values. In those cases, use default values, as below. In some problems, you are asked to use data sheet values for device parameters. In those cases, be certain that the data is not on the data sheet before using these default values.
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channel output conductance
parameter, lambda (MOSFETS) |
0 in DC calculations 1/(10 V) in AC calculations |
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MOSFET threshold voltage |
+0.3 V (NMOS), -0.3V (PMOS) |
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Va, Early voltage (BJTs) |
100 V. |
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beta (current gain of BJTs) |
100 |
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Vce(sat) (BJTs) |
0.5 V |
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Vbe(on) (BJTs) |
0.7 V |
Graded HW and Lab projects are obtained from the TAs. This will often be done online, but occasionally in paper form. Please see them during either office hours or during their lab hours.
Solutions will be posted on the online class administration web site by the TAs.
Please read the syllabus for procedures. Work in groups of 2 (not 3,4,...,27,..., 42,…).
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# |
what |
due |
files |
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1 |
elementary gain stage |
prelim. report: Jan 26 final report: Feb 2 |
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updates: |
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2 |
Multi-stage design |
prelim report: Feb 13 final report: Feb 23 |
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updates: |
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3 |
Operational-amplifier
design |
prelim report: March 2 checkoff: March 6 report: March 9 |
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updates: |
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Check-offs are by
appointment with the TAs |
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Design review contains: (1)
statement of design goals, (2) circuit diagram, (3) calculations proving that
the circuit will meet specifications. |
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The main text for the class is the online lecture notes- these are available via the links below.
It would also help to obtain a quality analog circuit design
text. If you don't have one, good choices include Fundamentals
of Microelectronics, by Behzad Razavi, Microelectronic
Circuit Design by R.C. Jaeger
and T.N. Blalock, or Analysis
and Design of Analog Integrated Circuits, by Grey, Meyer, and Lewis.
These books can be purchased online from many vendors. Older editions have the
advantage that used copies can be obtained at a lower price. Any of these books
would be just fine.
Each textbook covers the material in a
different way, and all these text books cover the material differently from the
lecture notes. It helps to have more than one perspective.
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Please read each note set
before attending lectures. It will then be much easier to follow the lectures
! |
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week |
set |
subject |
comment |
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1 |
bipolar transistor DC
characteristics |
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1 |
MOSFET DC characteristics |
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1-2 |
2abc review: small-signal models |
study if you have not
learned this. |
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1-2 |
2abc review: loadline analysis |
study if you have not
learned this. |
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2 |
elementary common-emitter
amplifier |
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2 |
degeneration, common-source
amplifier |
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3 |
source & emitter
followers |
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3 |
common-gate, common-base |
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4 |
multi-stage analysis |
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4 |
differential amplifiers,
current mirrors |
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5 |
MOS: multi-stage, mirrors, Darlingtons |
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6 |
multi-stage example
(bipolar) |
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6 |
MOS multi-stage example |
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7 |
MOS IC process flows. IC
design choices |
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7 |
Transistor-level design of
op-amps |
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8 |
Fourier transforms |
review of 130AB, 10ABC |
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9 |
LaPlace transforms |
review of 130AB, 10ABC |
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9 |
First-order circuits |
review of 130AB, 10ABC |
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10 |
RCL networks, 2nd-order circuits |
review of 130AB, 10ABC |
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material |
comment |
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you can bring this to the
exams. |
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dated, but seminal |
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hints for testing op-amps
for design projects |
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National Semiconductor
Linear Applications Handbook (please search on the web to find) |
Dated. Excellent tutorials,
many
written by the inimitable Bob Widlar |
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Please note: the solutions were composed during exam
grading. There are occasional errors in the solution, which were fixed during
grading, but the solution sheet may not have been updated. If in doubt, ask
the professor or the TAs. |
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year |
mid-term |
final |
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2014 |
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2014 |
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2015 |
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2015 |
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2017 |
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2017 |
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2019 |
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2021 |
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2022 |
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2023 |
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2025 |
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Type |
link |
comment |
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MOSFETs |
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small-signal matched pairs |
good for general analog
design at moderate frequencies. |
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small-signal arrays |
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small-signal array |
low (near zero) threshold
voltage. |
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medium-power |
high current devices, good
also as small-signal FETs at 1-100mA bias. At lower
currents, the data sheet does not provide data, and a curve-tracer must be
used |
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high-power |
Serve well as a
complementary power output stage DC-100kHz. |
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Bipolar Transistors |
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small-signal |
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matched pairs and arrays |
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Operational-amplifiers |
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5 V op-amps (single-dual,
quad) |
low-voltage, precision
op-amps |
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3MHz dual-supply op-amp |
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fast (80MHz)
op-amp |
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