Behrooz Parhami's website banner

Menu:

Behrooz Parhami's Web Page for PACT 2017 Workshop


Logo for PACT Workshop on Parallism in Computer Arithmetic

PARALLELISM IN COMPUTER ARITHMETIC:

From Circuits to GPU-Based Supercomputers


Page last updated on 2017 July 29

This September 9 workshop is co-located with the International Conference on Parallel Architectures and Compilation Techniques, Portland, OR, USA, September 9-13, 2017. PACT is co-sponsored by ACM SIGARCH, IEEE Computer Society, and IFIP (PACT Web site). The contact e-mail address is given in the banner above.

This workshop has been cancelled

In view of insufficient paper submissions, we have been forced to cancel the PACT workshop "Parallelism in Computer Arithmetic." We are considering other conferences on parallel processing as possible venues for a future version of the workshop. At this time, a prime candidate is IPDPS 2018, to be held in Vancouver, Canada, during May 21-25, with workshops being on its first and last days. The workshop proposal deadline is September 1. Please stay tuned.

Quick-Access Links

Reasons for Co-Location with PACT
Abstract (Theme and Goals)
Timeline for Participation
Program Committee
Panel Discussion
Workshop Proceedings

Reasons for Co-Location with PACT

Ever since the early days of digital computing, there has been a continuous flow of ideas about efficient parallel processing between computer arithmetic researchers and the parallel computation community. A striking example is the use of parallel-prefix computation techniques for systematic design of fast carry-lookahead adders and as an algorithmic primitive that facilitates the building of efficient parallel programs. Another example is circuit and compiler methods for fast multiplication and division by constants.

Abstract (Theme and Goals)

Some of the earliest parallel processing breakthroughs emerged from the quest for faster and higher-throughput arithmetic operations. Examples include carry-lookahead and several other fast addition algorithms, multi-operand addition, tree and array multipliers, recursive multiplication, convergence methods for division (and other functions of interest), arithmetic algorithms optimized for FPGA implementation, residue arithmetic, and modular operations on very wide operands for cryptographic applications. Additionally, the influence of arithmetic techniques on parallel computer performance can be seen in diverse areas such the bit-serial arithmetic units of early massively parallel SIMD computers, pipelining and pipeline-chaining in vector machines, design of floating-point standards to ensure the accuracy and portability of numerically-intensive programs, and prominence of GPUs in the design of today's most-powerful supercomputers. This workshop aims to provide a representative sample of the many interactions and cross-fertilizations between computer-arithmetic and parallel-algorithms communities by presenting historical perspectives, case studies of state of art and practice, and directions for further collaboration.

Timeline for Participation

Paper submission deadline: Friday, July 21, 2017 (submit via e-mail to B. Parhami; let him know if you need a brief extension)
Notification of acceptance: Friday, August 11, 2017
Final PDF paper for inclusion in the proceedings: Friday, August 25, 2017
Workshop held at PACT 2017: Saturday, September 9, 8:00 AM to 5:00 PM ((CANCELLED))

Program Committee

Parhami, Behrooz, organizer and chair (University of California, Santa Barbara, USA)
Jaberipur, Ghassem (Shahid Beheshti University and IPM, Tehran, Iran)
Muller, Jean-Michel (CNRS and ENS Lyon, France)
Swartzlander, Earl, Jr. (University of Texas, Austin, USA)

Panel Discussion

Topic and panelists TBA

Workshop Proceedings

TBA